Experienced power developers know that EMI suppression in the PCB designprocess can save a lot of time for EMI suppression design in the final process to the greatest extent. This article will explain to you the specification steps in PCB EMI design, interested friends come and have a look.
IC power processing
Ensure that the power PIN of each IC has a 0.1UF decoupling capacitor. For BGACHIP, a total of 8 capacitors of 0.1UF and 0.01UF are required at the four corners of BGA. The filter capacitor should be added to the power supply, such as VTT. This not only has an impact on stability, but also has a big impact on EMI.
Handling of clock lines
1) It is recommended to use the clock line first.
2) For clock lines with a frequency greater than or equal to 66M, the number of holes in each line shall not exceed 2, and the average shall not exceed 1.5.
3) For clock lines with a frequency less than 66M, the number of holes in each line shall not exceed 3, and the average shall not exceed 2.5
4) For a clock cable longer than 12 inches, if the frequency is greater than 20 m, the number of holes must not exceed 2.
5) If the clock cable has a hole, add a bypass capacitor between the second layer (stratum) and the third layer (power layer) at the adjacent position of the hole, as shown in Figure 2.5-1, to ensure that the high-frequency current loop of the reference layer (adjacent layer) is continuous after the clock cable is replaced. The power layer where the bypass capacitor resides must be the power layer through which the bypass capacitor passes, and be as close to the bypass capacitor as possible. The distance between the bypass capacitor and the bypass capacitor and the bypass capacitor should not exceed 300MIL.
6) In principle, all clock lines should not cross the island. Here are four ways to cross the island.
Cross island occurs between power island and power island. The clock line is routed at the back of the fourth layer. The third layer (the power layer) has two power islands, and the fourth layer must be routed across the two islands.
Cross island occurs between power island and ground island. The clock line is routed at the back of the fourth floor. There is an island in the middle of one of the power islands of the third floor (the power layer), and the fourth floor must be routed across both islands.
Transislets occur between geoislets and strata. In this case, the clock line is routed in the first layer, and there is an ground island in the middle of the second layer (stratum), and the first layer must be routed across the ground island, which means that the ground wire is interrupted.
There is no copper under the clock line. If it is impossible not to cross the island, ensure that the clock line with a frequency greater than or equal to 66M does not cross the island. If the clock line with a frequency less than 66M crosses the island, a decoupling capacitor must be added to form a mirror path. In Figure 6.1, for example, a 0.1UF capacitor is placed between two power islands and near the cross-island clock line.
When faced with the choice between two holes and one island, choose one island.
The clock line should be more than 500MIL away from the I/O side edge, and do not walk with the I/O line, if it is not possible, the distance between the clock line and the I/O port line should be greater than 50MIL.
When the clock line is on the fourth layer, the reference layer (power plane) of the clock line should be the power plane that supplies power to the clock as much as possible. The fewer hours that are referenced by other power planes, the better. In addition, the reference power plane of the clock line with a frequency greater than or equal to 66M must be 3.3V power plane.
The distance between clock lines should be greater than 25MIL.
The incoming and outgoing lines should be as far apart as possible when the clock lines are drawn. Try to avoid the wiring as shown in Figure A and Figure C. If the clock line needs to be replaced, avoid the wiring as shown in Figure E and use the wiring as shown in Figure F.
When the clock cable is connected to a device such as a BGA, if the clock cable is switched layers, avoid routing the clock cable as shown in Figure G, and do not route the hole under the BGA. It is better to route the clock cable as shown in Figure H.
Pay attention to the various clock signals, do not ignore any clock, including AUDIOCODEC AC_BITCLK, especially pay attention to FS3-FS0, although the name is not a clock, but actually running is a clock, should pay attention to.
ClockChip Pull-up Pull-down resistance as close to the ClockChip as possible.
I/O port processing
Each I/O port including PS/2, USB, LPT, COM, SPEAKOUT, GAME is divided into a piece of ground, the left and the right and the number is connected, the width is not less than 200MIL or three holes, other places do not connect with the number.
If the COM2 port is pin, get as close to the I/O site as possible.
I/O circuit EMI devices as close to I/OSHIELD as possible.
At the I/OPORT, the power layer and the ground are divided into separate islands, and the Bottom and TOP layers should be paved, and no signal is allowed to go through the island (the signal line is directly pulled out of the port, not the I/OPORT long-distance line).
A few notes
A. Design engineers shall strictly abide by EMI design specifications. EMI engineers shall have the right to inspect. If EMI design specifications are violated and EMI test fails, the responsibility shall be borne by design engineers.
B. The EMI engineer shall be responsible for the design specification. If the EMI test fails despite strict compliance with the EMI design specification, the EMI engineer shall provide the solution and summarize it in the EMI design specification.
E. MI engineer is responsible for EMI test of each peripheral port.
D. Each design engineer has the right to propose and question the modification of the design specification. EMI engineers have the responsibility to answer questions, and the engineers' suggestions are confirmed by experiments and then added to the design specification.
E. MI engineers are responsible for reducing the cost of EMI design and reducing the number of magnetic beads used.