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Engineering Technology
Engineering Technology
Crosstalk in PCB design
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Crosstalk in PCB design

The following suggestions can help designers reduce crosstalk in strip or mICros trip layouts:

Maintain maximum space between signal lines - limit wiring as much as possible. A general rule of thumb is to space signal wires at least three times the dielectric height or four times the wire width.


Keep the conductor of the transmission line as close to its ground plane as possible to tightly couple it to the ground plane and to decouple it from adjacent signals.


Critical networks can benefit by using differential routing techniques. This may require matching the length and gyration of each trace.

For substantial coupling, it may be helpful to route individual signals perpendicular to each other at different layers.


For single-ended signals, minimizing parallel run length helps reduce crosstalk. Use short parallel sections for wiring and avoid long coupLED sections between lines.

If it is not possible to change the distance between the two routes, reducing the distance between the routes and the ground formation to less than 10 mil can help reduce crosstalk.


Reduce the impact of ground rebound

With faster digital devices and reduced output switching times, device outputs exhibit higher transient currents when releasing load capacitors. In addition, there may be multiple outputs of a device that switch from high logic to low logic at the same time. The SIMultaneous dumping of current underground may temporarily raise the ground's electrical potential, causing a change in reference, a phenomenon known as ground rebound. The main conditions that affect grounding bounce include load capacitance, socket inductance, and the amount of simultaneous switching output.


Designers reduce ground rebound by:

Place holes near capacitor pads or use short, wide lines between them

Use wide and short wiring from the power supply pin to the power plane, island or decoupling capacitor. This reduces the possibility of ground bouncing by reducing the series inductance, and the transient voltage drops from the power supply pin to the power layer.

Connect each ground pin or through hole to the ground layer separately. Daisy chains cause a shared ground path, which increases the resistance and inductance of the loop current

Add decoupling capacitors as recommended by IC manufacturer. The decoupling capacitor must be as close to the device's power and ground pins as possible.

Move the switch output as close to the package ground pin as possible

Avoid pull-up resistors and use more pull-down resistors

Use multilayer PCBs with separate Vcc and GND planes so that the intrinsic capacitance of the VCC-GND plane is utilized

Use synchronous designs, as these are not affected by synchronous switch pins

The distance between the ground pin and the power pin is very close, which reduces mutual inductance because the current of the two pins goes in opposite directions.

Minimize inductance in decoupling capacitors by using a larger pass hole size on the capacitor pad

Minimize lead inductance by using surface mount capacitors

Use capacitors with low effective series resistance


Impedance matching and proper signal line terminating

Signals reflected back and forth along miSMAtched impedance lines produce a ringing at the load receiver. Ringing results in a false trigger of the receiver because it reduces the dynamic range of the receiver. Designers eliminate reflections by using appropriate signal line terminations so that the source impedance is equal to the line impedance and the load impedance.


In order to properly match the impedance and terminate the signal line, the designer can ensure signal integrity by:

Do not use over holes in clock transmission lines because over holes can cause impedance changes and produce reflections

Be straight. Do not use a right Angle bend, but a curved track

Use point-to-point clock routing whenever possible and end clock signals to minimize reflection

Use external devices to buffer load and limit load capacitance

Add 10 to 27 ohms of resistance in series at each switch output to limit current

Place the appropriate terminal resistance and ensure that the impedance match between the transmission line and the terminal is equal to the line impedance

Sandwich the layers of the clock track in the reference plane to minimize noise

Keep wire length below 5 cm, impedance below 65 ohms, and metal delay below 940 ps, inductance below 40 nH, wire capacitance below 20 pF, and total capacitance below 30 pF, especially for critical high speed wiring.



In addition to choosing suitable high-frequency materials, there are many better PCB layouts that designers can use to make them work properly at high frequencies. Since each PCB is unique, it must be customized for its application. Using PCB CAD or design suite software can help designers because the package offers a wide range of features.

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