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PCB factory: impedance matching and sharing in HDI PCB design
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PCB factory: impedance matching and sharing in HDI PCB design

PCB factory: impedance matching and sharing in HDI PCB design

Impedance matching is a way to configure load input impedance or its signal source output impedance. It is executed to achieve maximum power transmission and reduce signal reflection from the load. In other words, for proper impedance control, the load impedance must be equal to the characteristic impedance of the transmission line. When the transmitted signal is not reflected, it indicates that the load has absorbed all signals. Impedance matching in HDI is completely to avoid transmission failures, especially losses caused by resistance and PCB dielectrics.

Microwells can be used to create easy to produce PCB routing for impedance matching systems. BGA escape wiring technology and dog bone fan out structure can be used to achieve impedance matching in HDI.

When does PCB routing need impedance matching?

Impedance matching is determined by the steepness and rise/fall time of the signal, not by the frequency. If the rise/fall time of the signal (based on 10% to 90%) is less than 6 times of the trace delay, it is called a high-speed signal. Here, accurate impedance matching should be performed.

Challenges of HDI impedance matching

When implementing impedance matching in HDI, designers will encounter the following challenges:

In high-density interconnect designs, components have smaller pad to pad spacing, such as BGA. BGA with spacing less than or equal to 0.65 mm makes it challenging to route and control its width. In this case, via in pad and BGA escape routing technology can be used.

The vias in pads with blind holes are an advantage because they avoid via stubs, thereby improving signal integrity.

In HDI boards that require impedance control wiring, carefully designed routing and stacking are essential to ensure that impedance is consistent with signal standards.

Adjust the design line width for HDI impedance

The impedance of the wiring is determined by its width and height from the reference plane. In HDI boards with fine pitch BGA, carefully select the routing width and height to avoid routing between pads and through holes in pads.

Impedance control using BGA escape wiring in HDI PCB

Several BGA components are used when dealing with high-density interconnects. An escape routing scheme is required in order to route wires into and out of the bottom of the ball grid array with a high number of pins. In some cases, where controlled impedance is required (such as FPGAs and other high-speed components), BGA escape cabling can be challenging.

The escape routing strategy to be used when designing a circuit board largely depends on the BGA spacing, which defines the routing width allowed to be placed between solder balls. The fineness of the routing also depends on the manufacturer's limits, layer stacking and the necessary impedance. When choosing an escape routing scheme, keep the following guidelines in mind.

Escape routing technology for medium number of thin spacing BGA starts with necking method, because traces are routed in and out of BGA.

External wiring can be directly routed to the first row of pads on the circuit board.

The trace width of the second row of pads on the grid array is significantly reduced so that it can be installed between the first row of pads.

To reach the inner cushion of the remaining rows, go through the inner layer. Typically, each signal layer is routed to two lines, limiting both impedance and HDI crosstalk.

Dogbone fanout is the most popular BGA escape routing and fanout method (as shown in the figure below). This fanout technique helps to place through holes in pads closer to pads. Since the components are not directly welded to the pad through the through hole, filling plating is not required. 1 mm BGA and 0.8 mm BGA may be suitable for dog bone fanning.

circuit board

When the BGA spacing is less than 0.5 mm, the microvia in pad escape cabling technology is preferred. The micro via is placed directly in the pad, rather than routing small traces to the side of the pad. In order to prevent the solder core from absorbing to the back of the circuit board, the micropores are filled with conductive epoxy resin and plated with copper.

Microwells for BGA escape wiring

If the pad size (including the ring) is small enough for the fine spacing BGA, micro holes are used for internal BGA escape wiring. The following features distinguish micropores from conventional pores:

Length of vias: vias can only pass through one or two layers at most. If the standard thickness PCB has a very high number of layers, the through-hole can span more layers, but this requires additional manufacturing procedures. Stacked blind holes and buried holes crossing single layers shall be used as far as possible.

Micropore aspect ratio: Micropore aspect ratio (depth divided by diameter) shall be 0.75:1. Let's understand the same by considering an example of a 32 ply thick plate. Since the layer thickness (for 2-layer cores) is 2 mils, the diameter should not be less than 2.7 mils.

The micro through-hole can only be mechanically drilled to 8 mils safely, but because of frequent drilling breaks, the cost of drilling 8 mils of mechanical PCB can be close to the price of laser drilling. The throughput of mechanical through-hole is lower than that of laser drilling, because mechanical drilling must be carried out carefully to avoid bit breakage. Therefore, once you start using laser drilling, you will see a reduction in the total cost per plate.

To fan out with dog bones on a 0.8mm spacing BGA, the routing width must be 10 mils or less, and the micropores must be smaller (about 6 mils). For ball grid arrays with finer spacing (0.5 mm), use filled and plated solder pad inner holes to route to the inner layer through 7 mil or 8 mil. This will provide sufficient space between adjacent pads.

Regardless of the design style, the pores can be stacked or staggered to achieve the required wiring density. The requirements of IPC 6012 are adopted to ensure the optimal reliability of the size of the micropores and surrounding rings. The correlation of micro holes in pads in BGA escape routing can be understood by the fact that BGA spacing can be as low as 0.3 mm in some cases.

How to place blind holes for escape routing

Blind hole method of inner wiring space.

Blind hole is a valuable HDI design method, which can free up additional inner layer cabling space. When used between vias, these types of vias double the wiring space of the inner layer. It allows additional routing to connect pins on internal BGA lines.

With this method, a quarter of the signal layer is required to connect the high I/O BGA. Blind holes are placed in a cross, L-shaped or diagonal pattern to form a boulevard. The power and ground pin assignments determine which configuration is used.

Placing blind holes in a cross, L-shaped, or diagonal shape creates a boulevard on the inner layer to allow higher density routing and escape.

Explain: "Each layer can connect more routes, and the total number of signal layers can be reduced by using the boulevard to create additional cabling space. Blind holes are used to create four cross shaped boulevards. The newly designed boulevard provides 48 more escape routes (8 x 6 routes) per layer, and improves the signal integrity of internal routes. It allows the removal of two cabling layers and two reference planes."

In addition, he said, "On the secondary side of the circuit board, another advantage of using blind holes to create a boulevard can be observed. The through-hole spans the entire circuit board, but the boulevard is now open in BGA.

Fan out length and routing width

When using high-speed ICs, impedance is almost always a factor. The relationship between fan out wiring and impedance control comes into play when checking the length of the fan out section. Due to the routing length (if any) and parasitic capacitance/inductance of the via, the BGA fan out part will have its impedance.

First, check the signal bandwidth to determine whether the signal will pick up on the routing impedance. If the routing length is obviously smaller than the wavelength corresponding to the high end of the bandwidth, the routing part of the BGA fan can be ignored. The best method is to calculate the load impedance, which is a function of the length of the fan out route and the network input impedance created by the fan out route (after necking).

Use a 10% limit on the length required for the signal wavelength as a good approximation. A prudent 10% limit on digital signals with an inflection point frequency of 20GHz will result in a critical length of 0.73mm (stripline in the FR4 substrate). This means that larger ICs, such as FPGA, need to provide impedance matched fanouts for single ended and differential pairs.

The via inductance, the parasitic capacitance between the circuit board and the pad, and the pin inductance in the IC are critical. The low-pass T-filter circuit is composed of these parts. The 3dB cut-off frequency is only a typical figure that can be evaluated from the LC resonant circuit, provided that the through-hole inductance is set equal to the pin inductance. The T filter circuit is used as an impedance matching circuit to modify the output impedance of the driver IC.

A low-pass T-filter circuit with through hole inductance, parasitic capacitance between circuit board and bonding pad and pin inductance as main components.

If the impedance of the via part connecting the fanout trace to the internal trace is uncertain, the impedance matching of the fanout part is difficult. However, as long as the vias are short and span several layers directly, this fact can be ignored. The total input impedance, including via and internal routing, is determined by the internal routing impedance across a few layers. This is why through-hole impedance is usually not considered.

The main disadvantage is that high-speed BGA components (such as FPGAs) may need to be drilled back to remove the residual through-hole stubs below the BGA fan out. When HDI is used, very small diameter blind holes, buried holes and laser drilled micro holes (less than 6 mils according to IPC) are used, which eliminates back drilling and limits the through-hole inductance to the thickness of the spanning layer.

Since the layer thickness and the distance to the routing reference plane will decrease with the increase of the number of layers, the routing width must be reduced to compensate and maintain the impedance at an appropriate value. If you use differential pairs, consider routing coupling. In order to achieve impedance control, PCB design software with integrated field solver can help to design the correct routing width for HDI layer stack.

Why can't the wiring width be greater than the pad size?

The width of the wiring is proportional to its impedance and plays a crucial role when you enter the HDI state. The vias will become so small that once the routing width is small enough, they must be fabricated as micropores.

If the routing width of impedance control is too wide, either reduce the thickness of PCB laminate to reduce it, or increase the pad size. From the perspective of reliability, as long as the pad size exceeds the number specified in IPC standard, it is OK.

Create an impedance curve for the PCB stack and use this width as a design guide. After calculating the width required for impedance control, simply specify this value as the design rule. It is a good idea to perform crosstalk simulation for the recommended routing width to see if excessive crosstalk will occur.

Impedance matching in HDI is related to maintaining signal quality because components and wiring are closely spaced. Therefore, controlling impedance becomes an incredible task. Effective use of micropores is the key to impedance matching HDI systems. The escape wiring technology of finer spacing BGA and dog bone fan out method can be used to realize impedance matching in HDI. Circuit board design and circuit board processing manufacturers explain: how to share impedance matching methods in HDI PCB design.

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