Why can't the signal line be changed multiple times in high-speed **PCB design**? Everyone in PCB design must have touched the hole, so we all know that the hole has a great impact on the quality of **PCB signal**, first to introduce how we should choose the hole in PCB design.

There are usually three types of perforations to choose from: (in mil)

8/16±2mil 10/20±2mil 12/24±2mil

Usually, when the board is relatively dense, we will use 8/16±2mil(8/14,8/16,8/18) size holes, when the board is relatively empty, you can choose 12/24±2mil(12/22,12/24,12/26 can) size holes, 10/20±2mil(10/18,10/20,10/22) size holes can be used between 10/20. In terms of economic benefits, the larger the hole, the lower the cost, so we have to control the cost of the plate, while meeting our design, try to set the hole a little larger.

Of course, in HDI boards, we usually need to bury blind holes. Usually, the size of our blind hole ranges from 4/10±2 so that it can usually hit the pad, but it should be noted that it should not hit the center of the pad. It can usually hit the edge of the pad, which will be better in terms of process handling.

So is it better if we have a bigger hole or a smaller hole, which is obviously not the case.

From a process point of view, the inner diameter of our hole can not be less than 1/7 of the plate thickness, why?

Because when our hole is less than 1/7, due to the influence of process technology, we can not uniformly plated copper on the hole wall, when we can not uniformly plated copper, the electrical performance of our plate will be affected. Therefore, when the plate thickness is larger, we should also increase the hole.

Our conclusion above is that it's better to go through a bigger hole. At this point, we need to introduce you to two formulas. One is the calculation formula of the parasitic capacitance through the hole: C=1.41εTD2/ (D1-D) The other is the calculation formula of the parasitic inductance: L=5.08h[ln (4h/d) +1].

First look at the calculation formula of hole parasitic capacitance:

ε : the dielectric constant of the plate, usually the dielectric constant of different plates is different,

T: the thickness of the fingerboard.

Suppose the through-hole is in GND. In this case, D1 is the avoidance distance between the edge of the through-hole and the copper sheet (back pad). D2: refers to the outside diameter of the through-hole.

We can conclude from the above formula:

1. When the plate and plate thickness remain unchanged, the larger the parasitic capacitance of D, the smaller the parasitic capacitance, and the inversely proportional relationship between C and D1.

2. When the plate and thickness are unchanged, the larger the parasitic capacitance of D is, the larger the parasitic capacitance is, and the relationship between C and D2 is proportional.

3. In the case of constant plate thickness and D2,D, the larger the dielectric constant of the plate, the larger the parasitic capacitance, and C is proportional to ε.

4. The larger the dielectric constant and D2,D plate thickness T, the larger the parasitic capacitance. In the ordinary PCB design, the parasitic capacitance and parasitic inductance through the hole have little impact on the PCB design, and the conventional choice can be made. But at the speed. Through the analysis of the above parasitic characteristics of the hole, we can see that the middle hole design at high speed in the design of the PCB, seemingly simple holes often bring a huge negative impact on the circuit design.

In order to reduce the adverse effects of the parasitic effect of pores, it is possible to:

1) Select a reasonable hole size. For multi-layer general density PCB in the design, select 10/20/36POWER isolation area) through the hole is better; For the through-hole of the power supply or ground wire, a larger size can be considered to reduce the impedance;

2) The larger the POWER quarantine zone, the better;

3)** PCB signal wiring **should not be changed as far as possible, that is, to minimize holes;

4) The use of thinner PCB two parasitic parameters is conducive to reducing holes;

Of course, specific problems need to be analyzed in the design. Considering the cost and signal quality, at high speed PCB design, designers always want the hole as small as possible, the larger the wiring space on this template. In addition, the smaller the hole, the smaller its own parasitic capacitance, which is more suitable for high-speed circuits.

In the design of high-density PCB, the reduction of non-through hole (blind buried hole) and through hole size has brought about an increase in cost, and the through hole size can not be indefinitely reduced, affected by** PCB manufacturers **at high speed to limit drilling and electroplating and other process technology PCB should consider balance in the through hole design.

Then, after understanding the above information, we will know why in high-speed PCB design, we can not play too many holes. The hole itself will introduce parasitic capacitance and parasitic inductance. The more holes through, the greater the value of parasitic capacitance and parasitic inductance. So this is why many data manuals will write that the number of holes when we wire can not exceed how many, generally our high-speed signal line can not take more than three holes, can not punch the hole.