High-speed ADCs (analog/digital converters) are key analog processing elements in a variety of applications such as mass spectrometers, ultrasound, LiDAR/radar, telecommunications transceiver modules, etc. Whether the application is time-domain or frequency-based, the highest dynamic performance of the ADC is required. The faster and higher resolution ADC enables the ultrasonic system to have more detailed images and the communication system to have higher data processing capacity.
As sampling rates for 14-bit or higher resolution ADCs continue to increase into the 100-megabit sampling range, it follows that system designers must become experts in clock design and allocation and board wiring.
This paper describes some of the key issues in system design, with a special focus on printed circuit board (PCB) ground and power plane wiring technologies. Modern ADCs require modern PCB board designs. Without an accurate clock source or carefully designed PCB board wiring, high performance converters will fall short of their performance targets.
The single IF heterodyne receiver structure and advanced power amplifier linearization algorithms are placing demands on ADC performance. Such systems are pushing the converter's inherent jitter performance below 1/2 PS. Similarly, test instrument engineers need very low noise performance within broadband for advanced spectrum analyzer development.
Therefore, the most important subcircuit in a high-speed data conversion system is the clock source. This is because the timing accuracy of the clock signal will directly affect the dynamic performance of the ADC.
To minimize this effect, the ADC clock source must have very low timing jitter or phase noise. If this factor is not taken into account when selecting the clock circuit, the dynamic performance of the system will not be good. This has nothing to do with the quality of the front-end analog input circuit or the inherent jitter performance of the converter. Accurate clocks always provide along conversions at precise time intervals.
In fact, the clock arrives along continuously changing time intervals. Therefore, this timing uncertainty can be used to comprehensively evaluate the SNR of the sampled waveform through the data transformation process.
The maximum clock jitter is determined by:
Tj(rms)=(VIN(p-p) /VINFSR)× (1/(2(N+1)×π×fin)
If the input voltage (VIN) is equal to the full scale range (VINFSR) of the ADC, the jitter requirement becomes a factor of the ADC resolution (N bits) and the sampled input frequency (fin).
For the 70MHz input frequency, the total jitter requirement is:
Because many systems assign reference clocks via backplanes or separate connections, which can reduce signal quality, a local oscillator (low-phase noise VCXD) is usually used as the timing source for the ADC. Figure 1 shows timing generation using NS's LMX2531 clock synthesis. The LMX2531 connected to a timing generator is output by a programmable divider synthesizer, giving a jitter performance of less than 100 nanoseconds.
Proper grounding and selection of all signal routes are key to ensuring accurate signal conversion.
Separate ground plates work well for 50MSPS for 10-bit ADCs and 30 to 35MSPS for 12-bit ADCs. Beyond this range, additional circuit noise is noticeable, and separated floor plates can also cause signal radiation. When the line carries the current signal, problems occur at the separation between the plates.
Analog components are concentrated in the analog area of the board, and digital components are integrated in the digital area of the board. This keeps the analog and digital return currents away from each other. This is to isolate analog and digital ground currents, and to minimize ADC noise, but to ignore EMI effects. The analog component is concentrated in the analog area of the board, and the digital component is integrated in the digital area of the board. This keeps the analog and digital return currents away from each other. This is to isolate analog and digital ground currents, and to minimize ADC noise, but to ignore EMI effects. In addition, when the analog and digital power paths are controlled with a power trace, the return ADC current must depart from the output current path. This creates a current loop area that can radiate.
The use of separate ground panels and power panels can eliminate loop area problems and minimize radiation problems. This allows the output and return currents to flow close to each other while minimizing RFI/EMI problems. However, the placement of components into each other is very important, and common analog and digital return current paths in analog circuits can cause digital noise. We know that high frequency or high edge rate signals are mindful of high resistance, even in the ground plate where the analog and digital return currents need to be kept separate from each other.
Note that the proximity effect causes the output and return currents to flow as close to each other as possible. The return current path in the ground plate can be controlled by fine element placement and thoughtful routing of all stitches, including power lines. The ground return current will flow through the respective output trace, so it is possible to keep the analog and digital return currents away from each other.