There are many ways to solve EMI problems. Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression parts, and EMI SIMulation design. Starting from the most basIC PCB layout, this paper discusses the role and design skills of PCB layered stacking in controlling EMI radiation.
If a capacitor with appropriate capacity is reasonably placed near the power supply pin of the IC, the jump of the IC output voltage can be faster. However, the problem does not stop there. Due to the limited frequency response of the capacitor, it is impossible for the capacitor to generate the harmonic power required to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop at both ends of the inductance in the decoupling path, and these transient voltages are the main common mode EMI interference sources. How should we solve these problems?
As far as the IC on our circuit board is concerned, the power supply layer around the IC can be regarded as a good high-frequency capacitor, which can collect the energy leaked by the discrete capacitors that provide high-frequency energy for clean output. In addition, the inductance of the excellent power supply layer is SMAll, so the transient signal synthesized by the inductance is small, thereby reducing the common mode EMI.
Of course, the connection from the power supply layer to the IC power supply pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster. It is better to connect it directly to the bonding pad where the IC power supply pin is located. This should be discussed separately.
In order to control common mode EMI, the power supply layer should be conducive to decoupling and have a sufficiently low inductance. This power supply layer must be a pair of well-designed power supply layers. Some people may ask, how good is it? The answer to the question depends on the layering of the power supply, the materials between layers, and the operating frequency (that is, the function of IC rise time). Generally, the spacing between power layers is 6mil, and the interlayer is made of FR4 material, so the equivalent capacitance of each square inch of power layer is about 75pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100 to 300 ps, but according to the current development speed of IC, devices with a rise time of 100 to 300 ps will occupy a high proportion. For circuits with 100 to 300 ps rise time, 3 3mil layer spacing is no longer suitable for most applications. At that time, it was necessary to adopt the layering technology with layer spacing less than 1mil, and replace the FR4 dielectric material with a material with high dielectric constant. Now, ceramics and ceramic plastics can meet the design requirements of 100 to 300 ps rise time circuits.
Although new materials and methods may be used in the future, common mode EMI can be reduced to a very low level for today's common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials, which are usually sufficient to handle high-end harmonics and make transient signals low enough. The PCB layered stacking design example given in this paper will assume that the layer spacing is 3 to 6 mil.
From the point of view of signal routing, a good layering strategy should be to place all signal routing on one or several layers, which are close to the power layer or ground layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground plane, and the distance between the power layer and the ground plane should be as small as possible. This is what we call "layering" strategy.
What stacking strategies can help shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer and that single or multiple voltages are distributed in different parts of the same layer. The case of multiple power layers will be discussed later.
There are several potential problems in the design of 4-layer plates. First of all, for the traditional four layer plate with a thickness of 62mil, even if the signal layer is in the outer layer and the power and ground layers are in the inner layer, the distance between the power and ground layers is still too large.
If the cost requirement is the first, the following two alternatives to the traditional 4-layer board can be considered. Both schemes can improve the performance of EMI suppression, but they are only applicable to the situations where the density of components on the board is low enough and there is enough area around the components (to place the required power supply copper clad layer).
The first is the preferred solution. The outer layer of PCB is the stratum, and the middle two layers are the signal/power layer. The power supply on the signal layer is routed with a wide wire, which makes the path impedance of the power supply current low and the impedance of the signal microstrip path low. From the perspective of EMI control, this is the best 4-layer PCB structure available. The outer layer of the second scheme uses power and ground, and the middle two layers use signals. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as poor as that of the traditional 4-layer board.
If the routing impedance is to be controlLED, the above stacking schemes should be very careful to arrange the routing under the power supply and grounding copper island. In addition, the copper islands on the power supply or stratum shall be interconnected as much as possible to ensure the connectivity of DC and low-frequency.
If the component density on the 4-layer board is relatively large, it is better to use the 6-layer board. However, some stacking schemes in the 6-layer board design do not shield electromagnetic fields well enough, and have little effect on reducing the transient signal of the power bus. Two examples are discussed below.
In the first example, the power supply and ground are placed on the second and fifth layers respectively. Because of the high copper clad impedance of the power supply, it is very unfavorable to control common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.
In the second example, the power supply and ground are placed on the third and fourth layers respectively. This design solves the copper clad impedance problem of the power supply. Due to the poor electromagnetic shielding performance of the first and sixth layers, the differential mode EMI is increased. If the number of signal lines on the two outer layers is the least and the routing length is very short (shorter than 1/20 of the highest harmonic wavelength of the signal), this design can solve the differential mode EMI problem. If the component free and wiring free areas on the outer layer are filled with copper and the copper clad area is grounded (every 1/20 wavelength is an interval), the differential mode EMI is particularly well suppressed. As previously mentioned, the copper laying area shall be connected with the internal ground plane at multiple points.
In general, the first and sixth layers are arranged as strata, and the third and fourth layers are powered and grounded. Because there are two layers of double microstrip signal line between the power layer and the ground layer, the EMI suppression capability is excellent. The disadvantage of this design is that the routing layer has only two layers. As mentioned earlier, if the outer layer wiring is short and copper is laid in the area without wiring, the traditional 6-layer board can also achieve the same stacking.
Another 6-layer board layout is signal, ground, signal, power, ground and signal, which can realize the environment required for advanced signal integrity design. The signal layer is adjacent to the ground plane, and the power layer is paired with the ground plane. Obviously, the disadvantage is that the layers are stacked unevenly.
This usually brings trouble to processing and manufacturing. The solution to the problem is to fill all the blank areas of the third layer with copper. If the copper coating density of the third layer is close to the power layer or ground plane after copper filling, this board can be loosely regarded as a circuit board with balanced structure. Copper filling area must be connected to power or ground. The distance between connecting vias is still 1/20 wavelength. It is not possible to connect them everywhere, but they should be connected ideally.
10 ply board
Because the insulation isolation layer between multiple layers of boards is very thin, the impedance between layers of 10 or 12 layers of circuit boards is very low. As long as there is no problem with layering and stacking, excellent signal integrity can be expected. It is more difficult to process and manufacture 12 layers of boards according to the thickness of 62mil, and there are few manufacturers that can process 12 layers of boards.
Since there is always an insulating layer between the signal layer and the loop layer, it is not the best scheme to allocate the middle 6 layers to take the signal line in the 10 layer Board Design. In addition, it is important to make the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, ground and signal.
This design provides a good path for signal current and its loop current. The proper routing strategy is to route the first layer along the X direction, the third layer along the Y direction, the fourth layer along the X direction, and so on. Visually view the routing. The 1st and 3rd layers are a pair of layered combinations, the 4th and 7th layers are a pair of layered combinations, and the 8th and 10th layers are the last pair of layered combinations. When the routing direction needs to be changed, the signal line on the first layer should be changed to the third layer by "via". In fact, it may not always be so, but as a design concept, it should be followed as far as possible.
Similarly, when the signal routing direction changes, it should be from layer 8 and layer 10 or from layer 4 to layer 7 by via. This wiring ensures the closest coupling between the forward path and the loop of the signal. For example, if the signal is routed on layer 1, and the circuit is routed on layer 2 and only on layer 2, then even if the signal on layer 1 is transferred to layer 3 through "vias", the circuit is still on layer 2, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.
What if the actual routing is not like this? For example, the signal line on the first layer passes through the vias to the tenth layer. At this time, the loop signal has to find the grounding plane from the ninth layer, and the loop current must find the nearest grounding vias (such as the grounding pins of resistors or capacitors). If such vias happen to exist nearby, you are really lucky. If there is no such near via available, the inductance will become larger, the capacitance will be reduced, and the EMI will certainly increase.
When the signal wire must leave the current pair of wiring layers to other wiring layers through the vias, the grounding vias should be placed nearby the vias, so that the loop signal can return to the appropriate grounding layer smoothly. For the layering combination of layer 4 and layer 7, the signal circuit will return from the power layer or ground layer (i.e. layer 5 or layer 6), because the capacitive coupling between the power layer and ground layer is good, and the signal is easy to transmit.
Design of multiple power layers
If two power supply layers of the same voltage source need to output large current, the circuit board shall be arranged into two groups of power supply layers and grounding layers. In this case, an insulating layer is placed between each pair of power layers and the ground plane. In this way, we can get two pairs of power supply busbars with the same impedance that divide the current equally. If the impedance is not equal due to the stacking of power layers, the shunt will be uneven, the transient voltage will be much larger, and EMI will increase sharply.
If there are multiple power supply voltages with different values on the circuit board, multiple power supply layers are required accordingly. Remember to create a pair of power supply layers and ground layers for different power supplies. In the above two cases, when determining the position of the paired power layer and ground plane on the circuit board, remember the manufacturer's requirements for the balanced structure.
Since most of the circuit boards designed by engineers are traditional printed circuit boards with a thickness of 62mil, without blind holes or embedded holes, the discussion on layering and stacking of circuit boards in this paper is limited to this. For circuit boards with too large thickness difference, the layering scheme recommended in this paper may not be ideal. In addition, the delamination method in this paper is not applicable to PCB with blind holes or embedded holes due to different processing processes.
In circuit board design, thickness, via process and number of layers of circuit board are not the key to solve the problem. Excellent layered stacking is the key to ensure bypass and decoupling of power bus, minimize the transient voltage on the power layer or ground layer, and shield the electromagnetic field of signal and power supply. Ideally, there should be an insulation layer between the signal wiring layer and its loop grounding layer, and the matching layer spacing (or more than one pair) should be as small as possible. According to these basic concepts and principles, a circuit board that can always meet the design requirements can be designed. Now, the rise time of IC has been very short and will be shorter. The technology discussed in this paper is essential to solve the EMI shielding problem. PCB assembly and PCB processing manufacturers explain the role and design skills of PCB layered stacking in controlling EMI radiation.