Development of pcb production with parametrIC constraints
Nowadays, the factors considered in PCB design are more and more complex, such as clock, crosstalk, impedance, detection, manufacturing process, etc., which often makes designers repeat a lot of layout, routing, verification, maintenance and other work. The parameter constraint editor can incorporate these parameters into formulas, helping designers better handle these sometimes contradictory parameters in the design and production process.
At present, design software suppliers try to solve this problem by adding parameters to constraints. The most advanced part of this method is that it can specify the mechanical indicators that fully reflect various internal electrical characteristics. As long as they are added to the PCB design, the design software can use these information to control the automatic layout and routing tool.
When the subsequent production process changes, there is no need to redesign. The designer can automatically change the relevant constraints by SIMply updating the process characteristic parameters. The designer can then run DRC (Design Rule Check) to determine whether the new process violates other design rules, and find out which aspects of the design should be changed to correct all errors.
Constraints can be input in the form of mathematical expressions, including constants, various operators, vectors and other design constraints, providing a parametric rule driven system for designers. Constraints can even be input in the form of table lookup and stored in PCB or schematIC design files. PCB wiring, copper foil area location and layout tools should follow the constraint rules generated by these conditions. DRC verifies whether the entire design conforms to these constraints, including line width, spacing and space requirements (such as area and height restrictions).
A very simple example is the rise time constraint, which is generally set as a constant of 1.5ns. According to this condition, the constraint of the maximum routing length can be obtained, that is, 5800ml/ns is multiplied by the rise time of 1.5ns. A slightly more complex example is element spacing, which is determined by multiplying the tangent value of the detection angle by the device height. This formula can calculate the minimum element spacing value.
One of the main advantages of parametric constraints is that they can be handLED hierarchically. For example, the global line width rule can be used as a design constraint in the whole design. Of course, there will be individual regions or nodes that cannot follow this principle. In this case, you can bypass the higher-level constraint and adopt the lower level constraint in hierarchical design. Taking the Parameter Constraint Solver, the constraint editor of ACCEL Technologies, as an example, there are seven levels of constraints:
1. Design constraints are used for all objects without other constraints.
2. Hierarchical constraint, used for objects on a layer.
3. Node type constraint, used for all nodes included in a type.
4. Node constraint, used for a node.
5. Inter class constraint refers to the constraint between two types of nodes.
6. Space constraint, used for all devices in a space.
7. Device constraint, used for a device.
The software follows each design constraint in the order from individual devices to the whole design rules, and displays the application order of these rules in the design in a graphical way. PCB assembly and PCB processing manufacturers explain the use of parametric constraints for PCB design assistant PCB production development.