Explanation of aspects that should be paid attention to in PCB design evaluation
Let's look at some trends that force designers to re-examine their existing development tool capabilities and start ordering new ones:
The increase of semiconductor complexity and the total number of logic gates has required more pins and finer pin spacing for integrated circuits. It is very common to design more than 2000 pins on a BGA device with a pin spacing of 1mm, let alone to arrange 296 pins on a device with a pin spacing of 0.65mm. The need for faster rise times and signal integrity (SI) requires more power and ground pins, which requires more layers in the Multilayer board, thus driving the need for high-density interconnection (HDI) technology for micro vias.
HDI is an interconnection technology being developed in response to the above needs. Micro vias and ultra-thin dielectrics, thinner routing and SMAller line spacing are the main features of HDI technology.
2. RF design
For RF design, RF circuit should be directly designed into system schematic diagram and system board layout, rather than a separate environment for subsequent conversion. All SIMulation, tuning and optimization capabilities of the RF simulation environment are still necessary, but the simulation environment can accept more original data than the "actual" design. Therefore, the differences between data models and the problems of design transformation caused by them will disappear. First, designers can directly interact between system design and RF simulation; Secondly, if designers carry out a large-scale or quite complex RF design, they may want to assign circuit simulation tasks to multiple computing platforms running in parallel, or they may want to send each circuit in a design composed of multiple modules to their respective simulators to shorten the simulation time.
3. Advanced packaging
The increasing functional complexity of modern products requires a corresponding increase in the number of passive components, mainly reflected in the increase in the number of decoupling capacitors and terminal matching resistors in low power and high-frequency applications. Although the packaging of passive surface mount devices has shrunk considerably after several years, the results are still the same when trying to obtain the maximum limit density. Printed component technology has transformed from multi chip module (MCM) and hybrid module to SiP and PCB that can be directly used as embedded passive components today. In the process of transformation, the latest assembly technology was adopted. For example, an impedance material layer is included in a layered structure, and a series terminal resistor is directly used under the uBGA package, which greatly improves the performance of the circuit. Now, embedded passive components can obtain high-precision design, thus eliminating the additional processing steps of laser cleaning welds. Wireless components are also developing towards the direction of improving integration directly in the substrate.
In order to design a rigid flexible PCB, all factors that affect the assembly process must be considered. The designer cannot simply design a rigid flexible PCB as a rigid PCB, just as the rigid flexible PCB is just another rigid PCB. They must manage the bending area of the design to ensure that the design points will not cause the conductor to break and peel due to the stress action of the bending surface. There are still many mechanical factors to consider, such as minimum bending radius, dielectric thickness and type, sheet metal weight, copper plating, overall circuit thickness, number of layers, and number of bends.
Understand rigid flexible design and decide whether your product allows you to create a rigid flexible design.
5. Signal integrity planning
In recent years, new technologies related to parallel bus structure and differential pair structure for serial to parallel transformation or serial interconnection have been progressing.
The type of typical design problems encountered in a parallel bus and serial parallel conversion design. The limitation of parallel bus design lies in the change of system timing, such as clock skew and propagation delay. Due to clock skew across the bus width, it is still difficult to design timing constraints. Increasing the clock speed will only make the problem worse.
On the other hand, the differential pair architecture uses a swappable point-to-point connection at the hardware level to achieve serial communication. Usually, it transfers data through a one-way serial "channel", which can be stacked into 1 -, 2 -, 4 -, 8 -, 16 - and 32 width configurations. Each channel carries one byte of data, so the bus can handle data width from 8 bytes to 256 bytes, and can maintain data integrity by using some forms of error detection techniques. However, the high data rate leads to other design problems. Clock recovery in high frequency becomes a heavy burden for the system, because the clock needs to quickly lock the input data stream, and to improve the anti shake performance of the circuit, it also needs to reduce jitter between all cycles. Power noise also poses additional problems for designers. This type of noise increases the possibility of serious jitter, which will make eye opening more difficult. Another challenge is to reduce common mode noise and solve problems caused by loss effects from IC packaging, PCB boards, cables and connectors.
6. Design Suite Practicability
USB, DDR/DDR2, PCI-X, PCI Express, RocketIO and other design suites will undoubtedly help designers enter the new technology field. The design suite gives an overview and detaiLED description of the technology and the difficulties that designers will face, followed by simulation and how to create routing constraints. It provides explanatory documents together with the program, which provides a first opportunity for designers to master advanced new technologies.
It seems that it is easy to obtain a PCB tool that can handle PCB layout; But it is crucial to obtain a tool that can not only meet the layout but also solve your urgent needs.