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Common Problems and Solutions of Breaking the Bottleneck in High Speed PCB Design
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Common Problems and Solutions of Breaking the Bottleneck in High Speed PCB Design

Common Problems and Solutions of Breaking the Bottleneck in High Speed PCB Design

With the higher and higher operating frequency of devices, the signal integrity and other problems faced by high-speed PCB design have become a bottleneck of traditional design, and engineers are facing more and more challenges in designing complete solutions. Although the relevant high-speed simulation tools and interconnection tools can help designers solve some problems, the continuous accumulation of experience and in-depth exchanges between the industry are also needed in high-speed PCB design.

Here are some of the issues that have received wide attention.

Influence of Wiring Topology on Signal Integrity

When the signal is transmitted along the transmission line on the high-speed PCB board, it may cause signal integrity problems. Tongyang, a Netizen of STC, asked: For a group of buses (address, data, command) driving up to 4 or 5 devices (FLASH, SDRAM, etc.), when PCB wiring, whether the buses arrive at each device in turn, such as connecting to SDRAM first, then to FLASH... or whether the buses are star distributed, that is, separated from one place and connected to each device respectively. Which of the two methods is better in signal integrity?

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In this regard, Li Baolong pointed out that the impact of cabling topology on signal integrity is mainly reflected in the inconsistent arrival time of signals at each node, and the inconsistent arrival time of reflected signals at a node, which leads to deterioration of signal quality. Generally speaking, the star topology can make the signal transmission and reflection delay consistent by controlling several branches of the same length to achieve better signal quality. When using topology, consider the signal topology node, actual working principle and wiring difficulty. Different Buffers have different reflection effects on signals, so the star topology can not solve the problem of the above data address bus connection delay to FLASH and SDRAM, and thus can not ensure the signal quality; On the other hand, high-speed signals usually communicate between DSP and SDRAM, and the speed of FLASH loading is not high. Therefore, during high-speed simulation, it is not necessary to pay attention to the waveform at FLASH as long as the waveform at the node where the actual high-speed signal works effectively is ensured; Compared with daisy chain topology, star topology is more difficult to route, especially when a large number of data address signals adopt star topology.

Influence of pad on high-speed signal

In PCB, from the design point of view, a via is mainly composed of two parts: the middle drill hole and the pad around the drill hole. The engineer named fulonm asked the guests how pads affect high-speed signals. In this regard, Li Baolong said: pads have an impact on high-speed signals, which affects packaging of similar devices on devices. Detailed analysis shows that after the signal comes out of the IC, it reaches the transmission line through bonding wire, pin, package shell, bonding pad and solder. All joints in this process will affect the quality of the signal. But in actual analysis, it is difficult to give the specific parameters of pad, solder and pin. Therefore, they are generally summarized with the package parameters in the IBIS model. Of course, such analysis can be received at lower frequencies, but higher precision simulation for higher frequency signals is not accurate enough. A trend now is to use IBIS V-I and V-T curves to describe Buffer characteristics, and SPICE model to describe packaging parameters.

How to suppress electromagnetic interference

PCB is the source of electromagnetic interference (EMI), so PCB design is directly related to electromagnetic compatibility (EMC) of electronic products. If we pay attention to EMC/EMI in high-speed PCB design, it will help shorten the product development cycle and speed up the time to market. Therefore, many engineers paid close attention to the problem of electromagnetic interference suppression in this forum. For example, Shu Jian from Wuxi Xiangsheng Medical Imaging Co., Ltd. said that the harmonic of the clock signal exceeded the standard very seriously in the EMC test. Would you like to make special treatment to the power supply pin of the IC that uses the clock signal? At present, only the decoupling capacitor is connected to the power supply pin. What other aspects should be paid attention to in PCB design to suppress electromagnetic radiation? In this regard, Li Baolong pointed out that the three elements of EMC are radiation sources, transmission routes and victims. The transmission route is divided into space radiation transmission and cable transmission. So to suppress harmonics, first look at its propagation path. Decoupling of power supply is to solve the transmission of conduction mode. In addition, necessary matching and shielding are also required.

When answering questions from WHITE netizens, Li Baolong also pointed out that filtering is a good way to solve EMC radiation through conduction. In addition, it can also be considered from the aspects of interference sources and victims. In terms of interference sources, try to use an oscilloscope to check whether the rising edge of the signal is too fast and whether there is reflection or overshoot, undershoot or ringing. If there is, consider matching; In addition, the signal with 50% duty cycle shall be avoided as far as possible, because this signal has no even harmonics and more high-frequency components. For victims, measures such as land parcel can be considered.

Whether RF wiring is via or bent

In this forum, few netizens asked questions about high-speed analog circuit design. For example, a netizen of Jingheng Electronics asked: In high-speed PCB, passing can also reduce a lot of return paths, but some people said that they would rather bend than hit. How should they choose?

In this regard, Li Baolong pointed out that when analyzing the return path of RF circuit, it is different from the signal return in high-speed digital circuit. Both of them have something in common, they are distributed parameter circuits, and both of them apply Maxwell equation to calculate the characteristics of circuits. However, RF circuit is an analog circuit, in which two variables, voltage V=V (t) and current I=I (t), need to be controlled, while digital circuit only focuses on the change of signal voltage V=V (t). Therefore, in RF wiring, in addition to signal return, the influence of wiring on current should also be considered. That is, whether bending wiring and vias will affect the signal current. In addition, most RF boards are single-sided or double-sided PCBs with no complete plane layer. The return path is distributed around the signal and on the power supply. During simulation, 3D field extraction tools need to be used for analysis. At this time, the return flow of bending wiring and vias needs to be specifically analyzed; High speed digital circuit analysis generally only deals with multilayer PCBs with complete plane layers. 2D field extraction analysis is used. Only signal reflow in adjacent planes is considered, and vias are only processed as R-L-C of a lumped parameter.

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