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Analysis of common problems and solutions in high speed PCB design
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Analysis of common problems and solutions in high speed PCB design

With the increasing working frequency of devices, the problem of signal integrity in high-speed PCB design has become a bottleneck in traditional design, and engineers are faced with more and more challenges in designing a complete solution. In spite of

High-speed simulation tools and interconnect tools can help designers solve some of the problems, but high-speed PCB design also requires the accumulation of experience and in-depth communication between the industry.

The influence of wiring topology on signal integrity

Signal integrity issues may arise when signals are transmitted along transmission lines on high speed PCB boards. tongyang question: For a group of bus (address, data, command) drive up to 4, 5 devices (FLASH, SDRAM, etc.), in the PCB wiring, is the bus to each device in turn, such as first connected to SDRAM, then to FLASH...... Or the bus is star distributed, that is, separated from somewhere and connected to each device separately. Which of these two methods is better in terms of signal integrity?

The influence of wiring topology on signal integrity is mainly reflected in the inconsistent arrival time of signals at each node and the inconsistent arrival time of reflected signals at a certain node, which leads to the deterioration of signal quality. Generally speaking, the star topology can make the signal transmission and reflection delay consistent by controlling several branches of the same length, so as to achieve better signal quality. Between the use of topology, we should consider the signal topology node condition, the actual working principle and the difficulty of wiring. Different buffers have different effects on signal reflection, so the star topology cannot solve the delay of connecting the above data address bus to FLASH and SDRAM, and thus cannot ensure signal quality. On the other hand, high-speed signals are generally communicated between DSP and SDRAM, and the speed of FLASH loading is not high. Therefore, in high-speed simulation, as long as the waveform at the node where the actual high-speed signal works effectively is ensured, there is no need to pay attention to the waveform at FLASH. Compared with daisy-chain topology, star topology is more difficult to wire, especially when a large number of data address signals adopt star topology.

Influence of pad on high speed signal

In PCB, from a design point of view, a through hole is mainly composed of two parts: the drill hole in the middle and the pad around the drill hole. An engineer named fulonm asked the guest what effect the pad has on the high-speed signal. The pad has an effect on the high-speed signal, which is similar to the effect of the package of devices on the device. Detailed analysis, signal out from the IC, after the bonding line, pin, packaging shell, pad, solder to the transmission line, all joints in the process will affect the quality of the signal. But in the actual analysis, it is difficult to give the concrete parameters of pad, solder and pin. Therefore, the encapsulated parameters in the IBIS model are generally used to summarize them. Of course, such analysis can be received at lower frequencies, but for higher frequency signals, higher precision simulation is not accurate enough. There is a trend to use the V-I and V-T curves of IBIS to describe Buffer characteristics and SPICE models to describe encapsulation parameters.


How to suppress electromagnetic interference

PCB is the source of electromagnetic interference (EMI), so PCB design is directly related to electromagnetic compatibility (EMC) of electronic products. If we attach importance to EMC/EMI in high-speed PCB design, it will help shorten the product development cycle and accelerate the time to market. Therefore, many engineers in this forum very concerned about the suppression of electromagnetic interference. For example, Shu Jian from Wuxi Xiangsheng Medical Imaging Co., LTD., said that in EMC test, it was found that the harmonic of the clock signal exceeded the standard very seriously. May I ask whether special treatment should be done to the power pin of the IC that uses the clock signal? At present, only decoupling capacitor is connected to the power pin. What aspects should be paid attention to in PCB design to suppress electromagnetic radiation? The three elements of EMC are radiation source, transmission route and victim. The transmission channels are divided into space radiation transmission and cable conduction. So to suppress harmonics, first look at the way it travels. Power decoupling is the solution to conduction-mode propagation, in addition, the necessary matching and shielding is also required.

In answer to the question of user WHITE, we pointed out that filtering is a good way to solve the EMC radiation through the conduction pathway. In addition, interference sources and victims can also be considered. In terms of interference source, try to use oscilloscope to check whether the signal rising edge is too fast, there is reflection or Overshoot, undershoot or ringing, if so, you can consider matching; In addition, try to avoid doing 50% duty ratio signal, because this signal has no even harmonic, high frequency component more. In terms of victims, measures such as land cover can be considered.

RF wiring is to choose through hole or bending wiring

In this forum, there are no few users on high-speed analog circuit design questions. For example, a netizen of Jingheng Electronics asked: In high-speed PCB, it can also reduce a lot of backflow path, but some people say that they would rather bend than play, then how to choose?

Analysis of RF circuit backflow path, and high speed digital circuit signal backflow is not quite the same. Both of them have something in common: they are distributed parameter circuits, and they are the characteristics of circuits calculated using Maxwell equations. But the RF circuit is an analog circuit, voltage V=V(t), current I=I(t) two variables in the circuit need to be controlled, while the digital circuit only concerns the change of signal voltage V=V(t). Therefore, in RF wiring, in addition to considering signal reflux, it is also necessary to consider the effect of wiring on current. That is, whether the bending wiring and hole have any effect on the signal current. In addition, most RF boards are single-sided or double-sided PCB without a complete plane layer. The backflow path is distributed on various ground and power sources around the signal. 3D field extraction tool is needed for analysis during simulation. High speed digital circuit analysis generally only deals with multilayer PCB with complete plane layer. 2D field extraction analysis is used to consider only signal reflux in adjacent planes, and the hole is only treated as R-L-C of a lumped parameter.

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