If the high-speed PCB design can be as simple as connecting schematic nodes, and as beautiful as seen on the computer display, it will be a wonderful thing. However, unless designers are new to PCB design or extremely lucky, the actual circuit design is usually not as easy as what they are engaged in. PCB designers face many new challenges before the design can work normally and the performance is affirmed. This is exactly the current situation of high-speed PCB design -- the design rules and design guidelines are constantly developing. If you are lucky, they will form a successful solution.
Most PCBs are the result of mutual cooperation between schematic designers who are proficient in the working principle and mutual influence of PCB devices, as well as various data transmission standards that constitute the input and output of circuit boards, and professional layout designers who may know little or even may not know what will happen after converting small schematic wires into printed circuit copper wires. Usually, it is the schematic designer who is responsible for the success or failure of the final circuit board. However, the more schematic designers know about excellent layout technology, the more opportunities they have to avoid major problems.
If the design contains a high-density FPGA, it is likely that many challenges will be placed in front of the carefully designed schematic. Including the number of hundreds of input and output ports, the working frequency exceeding 500MHz (which may be higher in some designs), and the space between solder balls as small as half a millimeter, all of which will cause undue interaction between design units.
Concurrent switching noise
The first challenge is probably the so-called concurrent switching noise (SSN) or concurrent switching output (SSO). A large number of high-frequency data streams will cause ringing and crosstalk problems on the data line, and the ground wire bounce and power noise problems that affect the performance of the entire circuit board will also occur on the power supply and ground plane.
In order to solve ringing and crosstalk on high-speed data lines, it is a good first step to use differential signals. Since one line on the differential pair is the sink end and the other provides the source current, the inductive effect can be fundamentally eliminated. When data is transmitted using differential pairs, because the current is kept locally, it helps to reduce the "bounce" noise generated by the induced current in the return path. For RF frequencies up to hundreds of MHz or even several GHz, signal theory shows that the maximum signal power can be transmitted when impedance matches. When the transmission lines do not match well, reflection will occur. Only a part of the signal will be transmitted from the sender to the receiver, while other parts will bounce back and forth between the sender and receiver. The quality of differential signal realization on PCB will play a great role in impedance matching (and other aspects).
Differential routing design
The differential routing design is based on the principle of impedance controlled PCB. Its model is somewhat like coaxial cable. On a PCB with controlled impedance, the metal plane layer can be used as a shielding layer, the insulator is FR4 laminate, and the conductor is a signal wiring pair. The average dielectric constant of FR4 is between 4.2 and 4.5. Because the manufacturing error is not known, it may lead to excessive etching of copper wire, and eventually lead to impedance error. The most accurate method to calculate the PCB wiring impedance is to use the field analytic program (usually two-dimensional, sometimes three-dimensional), which requires the use of finite elements to directly solve the Maxwell equation for the entire PCB batch. The software can analyze EMI effect according to wire spacing, wire width, wire thickness and insulation layer height.
The 100 Ω characteristic impedance has become the industry standard value of the differential connecting line. The 100 Ω difference line can be made of two 50 Ω single ended lines of equal length. Because the two lines are close to each other, the field coupling between lines will reduce the differential mode impedance of the line. In order to maintain an impedance of 100 Ω, the width of the wiring must be reduced a little. As a result, the common mode impedance of each line in the 100 Ω differential line pair will be a little higher than 50 Europes.
Theoretically, the size of the wiring and the materials used determine the PCB impedance, but vias, connectors and even device pads will introduce impedance discontinuities in the signal path. It is usually impossible not to use these things. Sometimes, for more reasonable layout and wiring, it is necessary to increase the number of PCB layers, or add functions such as buried holes. The embedded hole only connects part of the PCB layers, but it also increases the production cost of the board while solving the transmission line problem. But sometimes there is no choice at all. As the signal speed becomes faster and faster, the space becomes smaller and smaller, and the additional requirements such as buried holes begin to increase, these should become the cost elements of PCB solutions.
Cross section is the most common pattern in the actual difference line layout. When ribbon wiring is used, the signal is clamped in the middle by FR-4 material. In the case of microstrip line, a conductor is exposed to the air. Because the dielectric constant of air is the lowest (Er=1), the top layer is most suitable for laying some key signals, such as clock signals or high-frequency SERIAL DESerial (SERDES) signals. The microstrip line wiring should be coupled to the lower ground plane, which reduces electromagnetic interference (EMI) by absorbing part of the electromagnetic field lines. In the stripline, all electromagnetic field lines are coupled to the upper and lower reference planes, which greatly reduces EMI. If possible, wide edge coupling stripline design should be avoided. This structure is easily affected by the coupling differential noise in the reference plane. In addition, PCB balanced manufacturing is also required, which is difficult to control. In general, it is relatively easy to control the line spacing on the same layer.
Decoupling and bypass capacitors
Another important aspect to determine whether the actual performance of PCB meets the expectations needs to be controlled by adding decoupling and bypass capacitors. Adding decoupling capacitors helps to reduce the inductance between the power supply of the PCB and the ground plane, and helps to control the signals on the PCB and the impedance of the IC. The bypass capacitor helps provide a clean power supply (providing a charge bank) to the FPGA. The traditional rule is that decoupling capacitors should be arranged anywhere convenient for PCB wiring, and the number of FPGA power pins determines the number of decoupling capacitors. However, the ultra-high switching speed of FPGA completely breaks this stereotype.
In a typical FPGA board design, the capacitor closest to the power supply provides frequency compensation for load current changes. In order to provide low-frequency filtering and prevent power supply voltage drop, large decoupling capacitors should be used. The voltage drop is due to the delayed response of the regulator when the design circuit starts. This large capacitor is usually an electrolytic capacitor with good low-frequency response, and its frequency response range is from DC to hundreds of kHz.
Each FPGA output change requires charging and discharging the signal line, which requires energy. The function of bypass capacitor is to provide local energy storage in a wide frequency range. In addition, small capacitance with small series inductance is required to provide high-speed current for high-frequency transient. The large capacitor with slow response continues to provide current after the energy of high-frequency capacitor is consumed.
A large number of current transients on the power bus increase the complexity of FPGA design. This current transient is usually associated with SSO/SSN. Inserting capacitors with very small inductance will provide local high-frequency energy, which can be used to eliminate switching current noise on the power bus. This decoupling capacitor that prevents high-frequency current from entering the device power supply must be very close to the FPGA (less than 1cm). Sometimes, many small capacitors are connected in parallel as local energy storage of devices, and can quickly respond to the changing demand of current.
In general, the wiring of the decoupling capacitor should be absolutely short, including the vertical distance in the vias. Even a little increase will increase the inductance of the wire, thus reducing the decoupling effect.
Other PCB technologies
With the improvement of signal speed, it is increasingly difficult to transmit data easily on the circuit board. Other technologies can be used to further improve the performance of PCB.
The first and most obvious method is simple device layout. It is common sense to design the shortest and most direct path for the most critical connection, but do not underestimate this point. Since the simplest strategy can achieve the best results, why bother to adjust the signal on the board?
Almost as brief is the way to consider the width of the signal line. When the data rate reaches 622MHz or even higher, the skin effect of signal transmission becomes more prominent. When the distance is long, the very thin routing on the PCB (such as 4 or 5 mils) will cause great attenuation to the signal, just like a low pass filter with attenuation that has not been designed, its attenuation will increase with the increase of frequency. The longer the backplane, the higher the frequency, and the wider the width of the signal line. For backplane routing with a length greater than 20 inches, the line width should reach 10 or 12 mils.
Usually, the most critical signal on the PCB is the clock signal. At that time, if the clock line is too long or not well designed, the jitter and offset will be amplified for the downstream, especially when the speed increases. You should avoid using multiple layers to transmit the clock, and do not have vias on the clock line, because vias will increase impedance changes and reflections. If it is necessary to deploy the clock with the inner layer, the upper and lower layers should use the ground plane to reduce the delay. When FPGA PLL is used in the design, the noise on the power plane will increase the PLL jitter. If this is critical, a "power island" can be created for the PLL. This island can use the thicker etching in the metal plane to isolate the PLL analog power supply from the digital power supply.
For signals with a rate of more than 2Gbps, a solution with higher cost must be considered. At such a high frequency, the thickness of the backplane and the design of the vias have a great impact on the integrity of the signal. The effect is better when the thickness of the back plate does not exceed 0.200 inch. When the PCB is a high-speed signal, the number of layers should be as small as possible to limit the number of vias. In thick plates, the vias connecting the signal layers are long, which will form transmission line branches on the signal path. Buried hole can solve this problem, but the manufacturing cost is very high. Another option is to use low loss dielectric materials, such as Rogers 4350, GETEK or ARLON. The cost of these materials may be nearly doubled compared with FR4 materials, but sometimes this is the only option.
There are other design techniques for FPGAs that provide some choice of I/O locations. In key high-speed SERDES designs, SERDESI/O can be isolated by reserving (but not using) adjacent I/O pins. For example, with respect to SERDESRx and Tx, VCCRX # and VCCTX #, as well as the ball position, the 3x3 or 5x5BGA ball area can be reserved. Or, if possible, keep the entire I/O group close to SERDES. If there is no I/O limitation in the design, these PCB technologies can bring benefits without increasing costs.
Finally, one of the best ways is to refer to the reference board provided by the FPGA manufacturer. Most manufacturers will provide the source layout information of the reference board, although special application may be required due to private information problems. These boards usually contain standard high-speed I/O interfaces, because FPGA manufacturers need these interfaces when characterizing and certifying their devices. Keep in mind, however, that these boards are usually designed for a variety of purposes and do not necessarily match specific design requirements. However, they can still be used as a starting point for creating solutions.