Analysis of signal reflection in high-speed PCB design

In high-speed PCB boards, routing is not just to connect two points. As a qualified engineer, wiring is a mixed knowledge carrier including resistance, capacitance and inductance. The signal line will reflect during transmission. It must be understood that the size of the load side reflection depends on the Z of the transmission line and the Z of the load.

The reflected signal is measured by the reflection coefficient KR. The reflection coefficient at the load end is: KRL=(ZL-Z0)/(ZL+Z0). For open circuit load, KRL=1; For short circuit load, KRL=- 1 is visible. For open circuit and short circuit load, the signal is 100% reflected back. A negative KRL value indicates that the reflected signal is in the opposite direction to the original signal. Similarly, the reflection size of the signal at the source end is expressed by the reflection coefficient at the source end: KRS=(ZS-Z0)/(ZS+Z0).

If the standard output level of the driver is 0.2V and the current is 24mA, the output impedance ZS is about 8.3 Ω. If the input impedance ZL of the load is greater than 100K Ω and far greater than Z0 (about 67 Ω), the reflection coefficient of the load end is KRL=1, and the signal is 100% reflected at the load end. The reflection coefficient at the source end is KRS=-0.78. Belonging to Qinji Group, Baineng is a leading electronic industry service platform in China. It provides online PCB components, sensor procurement, PCB customization, BOM distribution, material selection and other complete solutions for the electronic industry supply chain, meeting the comprehensive needs of small and medium-sized customers in the PCB industry in a one-stop manner.

Below is a detailed analysis of the driver's reflection process of generating a signal from 3.5V to 0.2V.

The first reflection: the driver voltage is 3.3V. According to the voltage division principle composed of ZS and Z0, the signal △ V generated on Z0 is -2.94V, and the source signal voltage is VS=O.56V. The reflection coefficient at the load end is 1. When the signal reaches the load end, VL=3.5-2.94-2.94=-2.38V.

The second reflection: the source end signal is 0.56V at the beginning. When the -2.94V signal reaches the source end, the second reflection occurs, and the reflection voltage is: VR=KPS * △ V=-0.78 * (-2.94)=2.29V. Therefore, the source terminal voltage becomes VS=0.56+(-2.94)+2.29=-0.09V.

The third reflection: when the second reflection signal reaches the load end, the load end voltage becomes VL=-2.38+2.29+2.29=2.2 V

In this transmission line with mismatched PCB impedance, the signal is reflected back and forth in this way, and its amplitude is reduced every time it is reflected, until it finally disappears. The vertical lines on the left and right represent the voltage at the source end and the load end respectively, and the diagonal lines indicate the voltage of the transmission signal and the reflected signal. It can also be used to represent the specific reflection process of the signal. One represents the source signal and the other represents the load signal. It can be seen that the signal transmitted to the load end drops below the input threshold after 5 cycles, and the transmission delay is generally between 6 and 16 ns/m. If the transmission delay tPD=10 ns/m, the delay through a 0.15 m PCB transmission line is about 1.5 ns, and the signal can be considered effective after being transmitted about 13.5 ns.