SDRAM Principle design and Layout Rules for PCB Design
Compared with the traditional SDRAM interface circuit, the design constraints of the registered SDARM circuit on the electrICal parameters of the circuit are relatively loose, and the driving ability of the main control chip is basically not considered in the design; However, since Registered SDRAM is also a high-speed interface circuit, its circuit design should also follow certain rules to ensure the reliability and stability of the designed circuit.
(1) Principle design rules
① The phase adjustment capacitor is designed at the clock input of each chip. The capacitance value can be set to 10pF, which can be adjusted according to the measured data.
② In the data pins of each SDRAM chip, the matching resistors are designed in series. The matching resistance value can be set to l0 Ω.
③ The latch clocks of each latch chip use different output clocks of the clock expansion circuit.
④ The input clock of each SDRAM chip uses different output clocks of the clock expansion circuit.
⑤ A series matching resistor is designed at the clock output pin of the clock expansion chip. The matching resistance value can be set to l0 Ω.
⑥ The output of the latch chip is designed with a matching resistor connected in series. The matching resistance value can be set to lO Ω.
(2) board Routing Rules
① SDRAM data cable: The data signal routing from MPC824l to the same SDRAM chip needs to be controlLED with equal length, and the length error should be controlled within ± 5%.
② SDRAM address/control line: latch chip to SDRAM
The address/control signal routing of the chip needs to be controlled with equal length, and the length error should be controlled within ± 5%.
③ The clock expansion circuit outputs the 2-way latch clock to the latch chip. Its routing needs to be controlled with equal length, and the length error is controlled within ± 27mm.
④ The clock expansion circuit outputs the 4-way clock to the SDRAM chip, and its routing needs to be controlled with equal length, and the length error is controlled within ± 1 Within 27 mm.
⑤ The address/control signal from the latch chip to the SDRAM chip is basically the same length as the clock line from the clock expansion circuit to the corresponding SDRAM chip, and the length error is controlled within ± 5%.
⑥ The feedback clock routing length of the clock expansion circuit is basically equal to the average clock routing length from the clock expansion circuit to the SDRAM chip, and the length error is controlled within ± 10%.
⑦ The routing length of data line, address line, control line and clock line between MPC824l and SDRAM chip is basically equal, and the length error is controlled within ± 10%.
(3) Layout Rules
① All phase regulating capacitors are placed near the receiving end.
② All clock series matching resistors are placed close to the sending end.
③ The serial matching resistance of the SDRAM chip data pin is close to the SDRAM chip.
④ The serial matching resistor at the output end of the latch chip is placed close to the output end.
(4) Other design rules
① Impedance control shall be carried out for each wiring, that is, 50 Ω impedance shall be used for single ended wires.
② The power supply pin of the chip must be equipped with a decoupling capacitor, with a capacity value of O one μ F。 In principle, each power pin must be designed with a decoupling capacitor and arranged as close to the power pin as possible.
③ Complete stratum and power supply layer shall at least ensure complete stratum.
④ The clock signal should go to the inner layer as far as possible to reduce EMI.
(5) Debugging of design circuit
The hardware pcb circuit designed according to the above rules can work stably under 100 MHz SDRAM clock only by slightly adjusting the phase adjustment capacitance. The range of phase regulating capacitance is generally 5~15pF. If the margin of timing parameters is sufficient, the phase regulating capacitor can also be left without welding. The circuit board manufacturer will explain the SDRAM principle design and layout rules of circuit board design.