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PCB Design
29Nov

# Differential pcb design, pair termination and distance from other signals

Pcb design difference line pair termination and distance from other signals

1 Distance between differential line pair and other signals

Controlling the distance between differential line pair and other signals can effectively reduce the interference of other signals on differential line pair and suppress EMI [1]. We know that the energy of the electromagnetic field decreases with the square of the distance. Generally, when the distance between the differential line pair and other signals is more than 4 times the width of the differential line or more than 3 times the distance between the differential line pair (whichever is greater), the influence between them is extremely weak and can be ignored. The formula is as follows:

50> 4w and L>3d,

Where, L: distance between differential line pair and other signals; w: Line width of difference line; d: The line spacing of the differential line pair.

Here, other signals include other differential lines, single ended lines, signal planes, etc. At the same time, the distance between the difference line pair and the edge of its reference plane should also be calculated in the above way, so as to ensure the symmetry of the two difference lines and reduce common mode noise, as shown in Figure 4.

2 Termination of differential pair

Adding termination resistance to differential line pair is an effective method to ensure impedance matching of differential transmission line. The control of terminal matching resistance shall select appropriate resistance network and load parallel connection according to different logic level interfaces to achieve the purpose of impedance matching [2].

At present, the most commonly used differential signals are LVDS and LVPECL. The following describes the termination methods of these two signals.

(1) LVDS signal

LVDS is a low swing differential signal technology, and its transmission rate is generally above several hundred Mb/s [3]. The driver of the LVDS signal consists of a current source that drives the differential line, usually 3.5 mA. Generally, the termination resistance should be bridged between positive and negative signals.

(2) LVPECL signal

LVPECL level signal is also one of the differential signal levels suitable for high-speed transmission, and its transmission rate can reach 1 Gb/s. Each single channel signal has a DC potential 2 V lower than the signal driving voltage, so the resistance can not be bridged between the positive and negative differential lines when terminal matching is applied, but each channel can only be matched at a single end.

It should be noted that with the development of microelectronics technology, many device manufacturers have been able to make the terminal matching resistance inside the device (which can be found in the chip manual) to reduce the work of PCB designers. At this time, the termination can no longer be carried out, otherwise the signal quality will be affected.

3 Other problems to be noted

In PCB design of differential line pair, the following issues should also be paid attention to: minimize the use of vias and other factors that cause impedance discontinuity; Do not use 90 ° polyline, instead, use arc or 45 ° polyline; If necessary, add ground plane isolation between different differential line pairs to prevent mutual crosstalk;

Do not just ensure that the total length of the wiring is equal, but try to ensure that each section of the wiring is equal (for the division of impedance discontinuities, such as sockets); If not necessary, try not to add test pads on the differential line.

4 Conclusion

Differential line pair has gradually become a common means in high-speed digital circuit design due to its excellent performance. In the design of high-speed digital PCB, differential line pairs are used to transmit high-speed signals. On the one hand, the signal integrity of PCB system is improved

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