High speed PCB board analogy for power integrity
The edge of the signal is getting faster and faster. Today's high-speed digital TV designers face problems that were unimaginable a few years ago For signal edge changes less than 1 nanosecond, the voltage between the power layer and the ground layer on the PCB is different anywhere on the circuit board, which will affect the power supply of the integrated circuit chip and cause logic errors on the chip To ensure the correct operation of high-speed equipment, the designer should eliminate such voltage fluctuations and maintain a low impedance distribution path To do this, you need to add decoupling capacitors to the circuit board to reduce noise generated by high-speed signals on the power supply and ground plane You must know how many capacitors to use, what the value of each capacitor should be, and where to put them on the blackboard On the one hand, you may need a lot of capacitors. On the other hand, the space on the circuit board is limited and valuable. These details determine the success or failure of the design
Trial and error design is time-consuming and expensive, which usually leads to over constrained design, thus adding unnecessary manufacturing costs. It is a more practical method to use software tools to simulate and optimize the circuit board design and the use of circuit board resources for the design of repeated operation tests for various circuit board configurations. This paper illustrates this process by designing an xDSM (Dense Subcarrier Multiplexing) circuit board for fiber/broadband wireless networks. The software simulation tool uses Ansoft's SIwave, which is based on hybrid full wave finite element technology and can directly import circuit board designs from the layout tools Cadence Allegro, Mentor Graphics BoardStation, Synopsys Encore and Zuken CR-5000 board designer. Figure 1 shows the PCB layout designed in SIwave. Since the structure of PCB is planar, SIwave can effectively conduct a comprehensive analysis. Its analysis output includes the resonance and impedance of the board, the s parameters of the selected network, and the equivalent Spice model of the circuit. The dimensions of the xDSM board (i.e. power and ground plane) are 11 x 7.2 inches (28 x 18.3 cm). Both the power layer and the grounding layer are 1.4mil thick copper foil separated by 23.98mil thick substrate. To understand the design of the circuit board, first, consider the bare board (no component installation) characteristics of the xDSM circuit board. According to the rise time of the high-speed signal on the circuit board, you need to understand the behavior of the circuit board in the frequency domain up to 2GHz. Figure 2 shows the voltage distribution when the circuit board excited by the sinusoidal signal resonates at 0.54GHz. Similarly, the circuit board resonates at 0.81GHz and 0.97GHz and above. For a better understanding, you can also simulate the voltage distribution between the power supply and the ground plane in resonant mode at these frequencies.
In the 0.54GHz resonant mode, the voltage difference between the power plane and the ground plane in the center of the circuit board becomes zero. This is also true for some higher frequency resonant modes. However, this is not true in all resonant modes. For example, in the high-order resonant modes of 1.07GHz, 1.64GHz and 1.96GHz, the voltage difference at the center of the circuit board changes non-zero. Finding the zero loss change point helps us to place the equipment that needs large current changes in a short time. For example, if a Xinlix FPGA chip is placed on a circuit board, the chip will generate an input current change of 2A within 0.2 nanoseconds. Such a large current change in a short time will lead to the power integrity problem of the circuit board, which will lead to various resonant modes of the circuit board, resulting in uneven voltage on the power layer and ground plane. However, some resonant modes have zero attenuation characteristics in the center of the circuit board. Therefore, placing FPGA chips here can avoid these low-frequency resonant modes on the circuit board. FPGA chips cannot excite these low frequency resonant modes because it is impossible to couple them from the center of the circuit board. The purple curve shows the resonance caused when the chip in the center of the circuit board draws current from the power plane. In fact, the peak value appears at the high order resonant frequencies of 1.07GHz, 1.64GHz and 1.96GHz, but not at the low order resonant frequencies of 0.54GHz, 0.81GHz and 0.97GHz as expected. The purple curve represents the resonance caused when the chip in the center of the circuit board absorbs current from the power plane; The green curve shows the response when the chip is off center.
Although device placement and placement can help reduce power integrity issues, they do not solve all problems. First of all, you can't put all the key components in the center of the circuit board. Generally, the flexibility of equipment placement is limited. Second, at any given location, some resonant modes will be excited. For example, the green curve in Figure 3 shows that 0.54GHz resonant mode will be excited when you move the chip off center along an axis. The key to the successful design of the circuit board PDS (power distribution system) is to add decoupling capacitors at appropriate locations to ensure the integrity of the power supply and ensure that the ground bounce noise is small enough within a wide enough frequency range.
Imagine an FPGA sinking 2A on the 0.2ns rising edge. At this time, the power supply voltage temporarily decreases (drops) and the ground plane voltage temporarily increases (the ground rebounds). The magnitude of change depends on the impedance of the circuit board and the decoupling capacitor used to provide current at the chip bias pin (Figure 4a). Since the transient value of current is 2A, the transient value of voltage changes from V=Z I Confirm that Z is the impedance seen from the chip end. In order to avoid voltage peak fluctuation, in the frequency range from DC to signal bandwidth, the value of Z must be lower than a certain threshold. The variation amplitude depends on the impedance of the circuit board and the decoupling capacitor used to provide current at the chip bias pin; To avoid voltage spikes, the Z value must be lower than a specific frequency in the frequency range from DC to the signal bandwidth. Threshold. The dotted line in the figure is the target area that PDS impedance should meet. In this design, in order to maintain the integrity of the power supply, the voltage fluctuation between the power supply and the ground must be kept within 5% of the 3.3 V standard value. In retrospect, the noise cannot be greater than 0.05 3.3V=165 mV。 According to this, the impedance of PDS can be calculated according to Ohm's law: 165mV/2A=82.5m Ω)
For frequency, it is usually 1 kHz or lower - the power supply meets the impedance characteristics, and the structure of the power supply and ground plane usually does not damage the impedance characteristics, because they show low resistance and inductance characteristics. When the frequency is higher than 1 kHz, the mutual inductance of the current path is large enough to cause the voltage to exceed the limit value. According to the higher frequency, the decoupling capacitor is necessary as a low impedance connection between the power plane and the ground plane. The signal bandwidth required to meet the PDS impedance requirements can be estimated by the following equation: In this design, its bandwidth is 1.75GHz.
In order to obtain such a wide bandwidth, it is usually necessary to place many high-frequency ceramic capacitors in the MHz signal area and large electrolytic capacitors in the kHz signal area. Together with other components, these capacitor matrices occupy valuable board space. In the trial and error design method, physical prototype is indispensable. Virtual prototype technology enables designers to solve this problem without physical prototype. PDS is designed for PCB board (such as xDSM board in this example), SIwave is used to place ports on IC chip, and input impedance of board is calculated within appropriate bandwidth. The red curve in Figure 5 shows the impedance when there is no capacitor on the circuit board. Both impedance axis and frequency axis adopt logarithmic coordinates. The simulation shows the influence of the capacitance of the circuit board itself, ignoring the low induced current loop through the power supply. It can be seen from the figure that the impedance increases with the decrease of frequency. However, since the loop through the power supply also has low impedance, this relationship is not strict. The red curve represents the impedance when there is no capacitor on the circuit board; The dark blue curve is the impedance characteristic after redesign; The light blue curve is the impedance curve after adding 10nF capacitor matrix; The color curve shows that 1nF capacitor matrix is added again. Results of. According to Z=1/(j · C), the straight line in the red curve indicates that the capacitance of the circuit board itself is 74nF. In order to keep the impedance at 82.5m Î at 1MHz © Below the target impedance, the capacitor value should be at least 2 µ F – almost 30 times the capacitance of the circuit board itself. To do this, 22 0.1mF capacitor matrices need to be added first. The dark blue curve in the figure is a redesigned impedance characteristic. In most frequency ranges, the design meets the requirements of impedance characteristics. However, at the high end of the bandwidth, the impedance curve does not meet the requirements of impedance characteristics due to the ESL (equivalent series inductance) and ESR (equivalent series resistance) of capacitors and the additional inductance caused by capacitor spacing. Since smaller capacitors have smaller ESL and ESR values, adding bypass can help improve their high-frequency characteristics. The light blue curve in Figure 5 is the impedance curve after adding another 10nF capacitor matrix. The green curve shows the result after adding 1nF capacitor matrix again. The addition of each capacitance matrix improves the impedance characteristics, but the results are still sufficient to meet the impedance characteristics. At this stage of design, the designer can add electromagnetic analogy while circuit analogy to complete the design. This approach allows designers to model the low voltage side impedance, including power load effects. It can also directly stimulate the noise on the power pin to directly verify the power plane noise and avoid unnecessary design overhead caused by over analyzing the power plane impedance.
Input and output ports should be added at the selected locations first. Add a port on the IC chip above, then add a port at the power input, and add two ports at the installation location of the other two chips. Then in SIwave, broadband scanning can be carried out to obtain 4x4 S parameter scattering matrix over the entire bandwidth. Then, full wave Spice can be used to generate circuit files compatible with Spice for further analysis in the circuit simulation environment. In the generated circuit file, the PCB board is located in the center of the circuit. The circuit archive also includes a model of the FPGA - a current source with a current probe and a differential voltage probe. The Spice circuit created by full wave Spice also includes the above three capacitor matrices. Adding a fourth capacitor matrix to the IC will further reduce the high side impedance. The circuit also includes a DC power supply with a small number of decoupling capacitors, ranging from 1nF to 100 µ F. It also includes models of two other IC chips, surrounded by a small array of 100nF capacitors.