High speed PCB design Guide

(1) Transmission line effect

The transmission line model based on the above definition, sums up, transmission line would be for the whole circuit design with the following effect.

· Reflected signals

· Delay & Timing errors

· Multiple False Switching across logic level threshold

· Overshoot/Undershoot of overshoot and undershoot

· Induced Noise (or crosstalk) Induced noise (or crosstalk)

· EMI radiation

1.1 Reflected Signal

If a line is not properly end (terminal), then from the drive end signal pulse is reflected on the receiving end, causing no expected effect, make the signal distortion. When significant distortion deformation can lead to a variety of errors, caused by design failure. At the same time, the distortion distortion signal is more sensitive to noise, which will also cause the design failure. If the above situation is not considered enough, EMI will increase significantly, which will not only affect the design results, but also cause the failure of the entire system.

The main reason of reflection signal: too long running; Transmission lines with unmatched terminations, excess capacitance or inductance, and impedance mismatches.

1.2 Delay and timing errors

Signal delay and timing errors are represented by keeping the signal unchanged for some time as it changes between high and low thresholds of the logic level. Excessive signal delay may lead to timing errors and confusion of device functions.

Problems often occur when you have more than one receiver. The circuit designer must determine the worst-case time delay to ensure that the design is correct. Cause of signal delay: drive overload, too long cable.

1.3 The logical level threshold has been crossed for several times

The signal may cross the logic level threshold several times during the jump process, resulting in this type of error. Multiple crossing of the logic level threshold error is a special form of signal oscillation, that is, the signal oscillation occurs near the logic level threshold. Multiple crossing of the logic level threshold will result in logic dysfunction. Causes of reflected signals: excessively long lines, unterminated transmission lines, excessive capacitance or inductance, and impedance mismatch.

1.4 Overshoot and undershoot

Overshoot and undershoot are caused by either too long wiring or too fast signal change. Although most components are protected by input protection diodes at the receiver end, sometimes these overshoot levels can go well beyond the component supply voltage range, damaging the component.

1.5 crosstalk

Crosstalk is represented as when a signal passes on one signal line, the signal adjacent to it will be induced on the PCB board, which is called crosstalk.

The closer the signal cables are to the ground wire, the greater the distance between the cables, and the smaller the crosstalk signal generated. Asynchronous signals and clock signals are more prone to crosstalk. Therefore, the way to solve the crosstalk is to remove the crosstalk signal or shield the seriously interfered signal.

1.6 the electromagnetic radiation

Electro Magnetic Interference (EMI) is a problem caused by excessive electromagnetic radiation and sensitivity to electromagnetic radiation. EMI means that when the digital system is powered on, it will radiate electromagnetic waves to the surrounding environment, thus interfering with the normal operation of the surrounding electronic equipment. The main reason is that the circuit working frequency is too high and the layout is unreasonable. At present, there are software tools for EMI simulation, but EMI emulators are very expensive and the setting of simulation parameters and boundary conditions is difficult, which will directly affect the accuracy and practicability of simulation results. The most common practice is to control the EMI design rules applied in each part of the design, to achieve the rule driving and control in each part of the design.

(2) Methods to avoid transmission line effect

In view of the influence brought by the above transmission line problem, we discuss the following ways to control these effects.

2.1 Strictly control the length of key network cables

If there are high speed jumping edges in the design, the problem of transmission line effect on PCB board must be taken into account. This is especially true of the fast integrated circuit chips with high clock frequencies that are now commonly used. There are some basic principles for solving this problem: If the design is done with CMOS or TTL circuits, the operating frequency is less than 10MHz, and the wiring length should be no more than 7 inches. Operating frequency at 50MHz wiring length should not be greater than 1.5 inches. The wiring length should be 1 inch if the operating frequency is at or above 75MHz. The maximum wiring length for GaAs chips should be 0.3 inches. If more than this standard, it has the problem of transmission line.

2.2 the topology of the reasonable planning walk line

Another way to solve the transmission line effect is to choose the correct wiring path and terminal topology. The routing topology refers to the routing sequence and structure of a network cable. When a high-speed logic device is used, the rapidly changing edge signal will be distorted by the branch route of the signal trunk unless the branch length is kept very short. In general, PCB routing adopts two basic topologies, namely Daisy Chain routing and Star distribution.

For Daisy chain wiring, wiring from the driving end, in order to reach the receiver. If a series resistor is used to change the signal characteristics, the series resistor should be located next to the driving end. Daisy chain routing has the best effect in controlling the interference of high order harmonics. However, this routing mode has the lowest rate of distribution and is not easy to 100% distribution. In the actual design, we make the branch length of Daisy chain wiring as short as possible, and the safe length value should be: Stub Delay < = Trt *0.1.

For example, the length of the branch end in a high-speed TTL circuit should be less than 1.5 inches. This topology structure takes the wiring space smaller and use a single end resistance matching. But this kind of linear structure makes in different signals at the receiving end of receiving is out of sync.

The star topology can effectively avoid the problem of clock signal asynchronism, but it is very difficult to finish the wiring manually on the high density PCB board. The best way to complete star routing is to use automatic routing device. Each branch requires termination resistors. The resistance value of the terminal resistance should match the characteristic impedance of the line. This can be done manually or by CAD tools to calculate the characteristic impedance value and the terminal matching resistance value.

In the two examples above, a simple terminal resistor is used, but in practice you can choose to use a more complex matching terminal. The first option is the RC matching terminal. RC matching terminal can reduce power consumption, but only used in the case of stable signal operation. This method is most suitable for clock line signal matching processing. The disadvantage is that the capacitance in RC matching terminal may affect the shape and propagation speed of the signal.