How to Use parameterized constraints for PCB design?

In recent years, the requirements for PCB layout have become more and more complex, and the number of transistors in integrated circuits has continued to rise at the rate predicted by Moore's Law, resulting in faster devices and shorter uptime per pulse, as well as an increasing number of pins - often 500 to 2,000 pins. All of this leads to density, clock, and crosstalk issues when designing PCBS.

Today's PCB design considerations are increasingly complex, such as clock, crosstalk, impedance, detection, manufacturing process, and so on, which often makes PCB designers have to repeat a lot of routing, verification, and maintenance work. The parameter constraint editor can encode these parameters into formulas to help PCB designers better deal with these sometimes even contradictory parameters during PCB design and production.

A few years ago, most PCBS had only a few "critical" nodes (Nets), usually defined as constraints on impedance, length, and clearance. PCB designers typically routed these lines manually and then automatically routed the entire circuit on a large scale using software. Today's PCBS often have 5,000 or more nodes, of which more than 50% are critical nodes. Due to the pressure of market time, manual wiring is impossible at this time. In addition, not only does the number of critical nodes increase, but also the constraints on each node.

These constraints are mainly due to the correlation of parameters and the increasing complexity of PCB design requirements. For example, the interval between two routes may depend on a function related to both node voltage and circuit board material. The reduction of digital IC rise time will have an impact on both high and low clock speed PCB designs. Because the pulse is generated faster, the establishment and hold time is shorter. In addition, the interconnect delay as an important part of the total delay of high speed PCB design is also very important for low speed PCB design.

Some of these problems would be easier to solve if boards were bigger, but the trend is the other way around. Due to the requirements of interconnection delay and high density packaging, circuit boards are becoming smaller, resulting in high density circuit PCB design, and must follow the design rules of miniaturized PCB. Coupled with these miniaturized PCB design rules, the problem of crosstalk noise becomes more and more acute, and the problems of crosstalk, switching noise, and ground bounce are exacerbated by the ball-grid arrays and other high-density packages themselves.

Fixed constraint A constraint that exists

The traditional approach to these problems has been to translate electrical and process requirements into fixed constraint parameters by rule of thumb, default values, numerical tables or calculation methods. For example, an engineer designing a PCB circuit may first determine a rated impedance and then "estimate" a rated line-width to meet the required impedance based on the final process requirements, or test interference using a spreadsheet or arithmetic program and then calculate the length constraints.

This approach usually requires the PCB design to produce a set of empirical data as the basic guidelines for PCB designers, so that these data can be used in PCB design with automatic layout tools. The problem with this approach is that empirical data is a general principle. Most of the time they are correct, but sometimes they don't work or lead to the wrong results.

Let's look at the error that can be caused by this method using the example of determining impedance above. Factors related to impedance include dielectric characteristics of the circuit board material, copper foil height, distance between layers to ground/power layer and line width. Since the first three parameters are generally determined by the production process, PCB designers usually rely on line width to control impedance. Since the distance from each line layer to the ground or power layer is different, it is obviously wrong to use the same empirical data for each layer. The problem is compounded by the fact that the manufacturing process or the characteristics of the board can change at any time during development.

Most of the time, these problems will be exposed during the prototype production stage, which is usually solved by repairing the circuit board or re-designing the PCB. This is costly, and fixes often bring additional problems that require further debugging, and ultimately the loss of revenue due to delayed time to market far exceeds the debugging cost. This problem, faced by almost every electronics manufacturer, ultimately comes down to the fact that traditional PCB design software cannot keep up with the current electrical performance requirements, which is not as simple as the empirical data of mechanical PCB design.