Summary of high-speed PCB design rules and cause analysis

Summary of high-speed PCB design rules and cause analysis

1. When the clock frequency of PCB exceeds 5MHZ or the signal rise time is less than 5ns, a multilayer board design is generally required.

Cause: The area of the signal circuit can be well controlled by using the multilayer board design.

2. For multilayer boards, the key wiring layer (the layer where clock line, bus, interface signal line, RF line, reset signal line, chip selection signal line and various control signal lines are located) should be adjacent to the complete ground plane, preferably between two ground planes.

Reason: The key signal lines are generally strong radiation or extremely sensitive signal lines. Wiring close to the ground plane can reduce the area of the signal circuit, reduce its radiation intensity or improve the anti-interference ability.

3. For single-layer boards, both sides of key signal lines shall be wrapped.

Reason: The two sides of the key signal are grounded, which can reduce the area of the signal loop on the one hand, and prevent the crosstalk between the signal line and other signal lines on the other hand.

4. For the double-layer board, the projection plane of the key signal line has a large area of flooring, or it is wrapped with holes as the single panel.

Cause: It is the same as the key signal of the multilayer board close to the ground plane.

5. In the multilayer board, the power plane shall be reduced by 5H-20H relative to its adjacent ground plane (H is the distance between the power and ground plane).

Cause: Shrinking the power plane relative to its return ground plane can effectively suppress the edge radiation problem.

6. The projection plane of the wiring layer should be within the region of its return plane layer.

Cause: If the wiring layer is not within the projection area of the return plane layer, it will cause edge radiation problems, and increase the area of the signal loop, which will lead to increased differential mode radiation.

7. In the multilayer board, the TOP and BOTTOM layers of the single board should have no signal lines larger than 50MHZ.

Reason: It is better to walk the high-frequency signal between two plane layers to inhibit its radiation to space.

8. For boards with a board level operating frequency greater than 50MHz, if the second layer and the penultimate layer are wiring layers, the TOP and BOOTTOM layers should be paved with grounding copper foil.

Reason: It is better to walk the high-frequency signal between two plane layers to inhibit its radiation to space.

9. In multilayer boards, the main working power plane (the most widely used power plane) of a single board should be close to its ground plane.

Cause: The power plane adjacent to the ground plane can effectively reduce the loop area of the power circuit.

10. In a single layer board, there must be a ground wire adjacent to and parallel to the power line.

Cause: Reduce the area of power current loop.

11. In the double-layer board, there must be a ground wire adjacent to and parallel to the power line.

Cause: Reduce the area of power current loop.

12. In the layered design, the adjacent settings of the wiring layer shall be avoided as far as possible. If the adjacent wiring layers cannot be avoided, the layer spacing between the two wiring layers should be appropriately increased, and the layer spacing between the wiring layers and their signal circuits should be reduced.

Cause: Parallel signal routing on adjacent wiring layers will cause signal crosstalk.

13. Adjacent plane layers shall avoid overlapping their projection planes.

Cause: When the projection overlaps, the coupling capacitance between layers will cause the noise between layers to be coupled.

14. During PCB layout design, the design principle of straight line placement along the signal flow direction shall be fully followed to avoid looping back and forth as much as possible.

Cause: Avoid direct coupling of signals, which affects signal quality.

15. When multiple module circuits are placed on the same PCB, digital circuits and analog circuits, high-speed and low-speed circuits shall be arranged separately.

Cause: Avoid mutual interference between digital circuits, analog circuits, high-speed circuits and low-speed circuits.

16. When there are high, medium and low speed circuits on the circuit board at the same time, the high and medium speed circuits should be kept away from the interface.

Cause: Prevent high-frequency circuit noise from radiating outward through the interface.

17. Energy storage and high-frequency filter capacitors shall be placed near unit circuits or devices with large current changes (such as input and output terminals of power modules, fans and relays).

Cause: The existence of energy storage capacitor can reduce the loop area of high current loop.

18. The filter circuit of the power input port of the circuit board shall be placed close to the interface.

Cause: Avoid the lines that have been filtered from being coupled again.

19. On the PCB board, the filtering, protection and isolation devices of the interface circuit should be placed close to the interface.

Cause: It can effectively achieve the effects of protection, filtering and isolation.

20. If there are both filtering and protection circuits at the interface, the principle of protection before filtering shall be followed.

Cause: The protection circuit is used for external overvoltage and overcurrent suppression. If the protection circuit is placed behind the filter circuit, the filter circuit will be damaged by overvoltage and overcurrent.

21. The layout shall ensure that the input and output lines of the filter circuit (filter), isolation circuit and protection circuit are not coupled with each other.

Cause: When the input and output wiring of the above circuits are coupled with each other, the filtering, isolation or protection effects will be weakened.

22. If the interface "clean" is designed on the board, the filter and isolation devices should be placed on the isolation belt between the "clean" and the working place.

Cause: Avoid mutual coupling of filter or isolation devices through the plane layer to weaken the effect.

23. No other devices except filter and protective devices can be placed on the "clean ground".

Reason: "Clean" design aims to ensure minimum interface radiation, and "clean" is easily coupled by external interference, so there should be no other irrelevant circuits and devices on the "clean".

24. Crystals, crystal oscillators, relays, switching power supplies and other strong radiation devices shall be at least 1000 mils away from the board interface connector.

Cause: The interference will radiate outward directly or couple the current on the outgoing cable to radiate outward.

25. Sensitive circuits or devices (such as reset circuits, WATCHDOG circuits, etc.) shall be at least 1000 mils away from the edges of boards, especially the edges of board interfaces.

Cause: Places like the board interface are most susceptible to external interference (such as static electricity) coupling, while sensitive circuits such as reset circuit and watchdog circuit are very likely to cause system misoperation.

26. Each filter capacitor for IC filtering shall be placed as close as possible to the power supply pin of the chip.

Cause: The closer the capacitor is to the pin, the smaller the area of the high-frequency circuit, and thus the smaller the radiation.

27. The matching resistor in series at the starting end shall be placed close to its signal output end.

Cause: The design purpose of the series matching resistance at the beginning is to make the sum of the output impedance of the chip output end and the impedance of the series resistance equal to the characteristic impedance of the wiring. The matching resistance is placed at the end, which cannot meet the above equation.

28. PCB wiring shall not have right angle or acute angle wiring.

Cause: The right angle wiring leads to discontinuous impedance, leading to signal transmission, resulting in ringing or overshoot, forming strong EMI radiation.

29. Avoid layer setting of adjacent wiring layers as much as possible. If it cannot be avoided, try to make the routing in the two wiring layers perpendicular to each other or the parallel routing length less than 1000 mils.

Cause: reduce crosstalk between parallel lines.

30. If the board has an internal signal routing layer, the clock and other key signal lines are laid in the inner layer (the routing layer is preferred).

Cause: The key signals can be shielded by laying them on the internal wiring layer.

31. It is recommended to wrap the ground wire on both sides of the clock wire, and the grounding via should be punched every 3000mil.

Cause: ensure that the potential of each point on the grounding wire is equal.

32. Clock, bus, RF cable and other key signal wiring: other parallel wiring on the same layer shall meet the 3W principle.

Cause: Avoid crosstalk between signals.

33. The bonding pads of surface mounted fuses, magnetic beads, inductors and tantalum capacitors used for power supply with current ≥ 1A shall be connected to the plane layer through at least two vias.

Cause: reduce the equivalent impedance of vias.

34. The differential signal lines shall be laid in the same layer, of equal length and in parallel, with the same impedance and no other lines between the differential lines.

Reason: ensure the common mode impedance of differential line pair is equal, and improve its anti-interference capability.

35. The key signal routing must not cross the partition area (including the reference plane gap caused by vias and pads).

Cause: Wiring across the partition will lead to an increase in the area of the signal loop.

36. When it is unavoidable that the signal line is separated from the ground across its return plane, it is recommended to use bridge capacitance near the signal cross division, and the capacitance value is 1nF.

Cause: When the signal is split across, the circuit area is often increased. The bridge grounding method is used to set the signal circuit for it manually.

37. No other irrelevant signals shall be routed below the filter (filter circuit) on the board.

Cause: Distributed capacitance will weaken the filtering effect of the filter.

38. The input and output signal lines of the filter (filter circuit) shall not be parallel or crossed.

Cause: Avoid direct noise coupling before and after filtering.

39. The distance from the key signal line to the edge of the reference plane is ≥ 3H (H is the height of the line from the reference plane).

Cause: inhibit the edge radiation effect.

40. For metal shell grounding element, the top layer of its projection area shall be paved with grounding copper sheet.

Cause: The distributed capacitance between the metal shell and the grounding copper sheet is used to restrain its external radiation and improve its immunity.

41. In the single layer board or double layer board, attention should be paid to the "loop area minimization" design when wiring.

Cause: The smaller the loop area is, the smaller the external radiation of the loop is, and the stronger the anti-interference ability is.

42. When the signal lines (especially the key signal lines) change layers, they should be designed to pass holes near the layer change holes.

Cause: It can reduce the area of signal loop.

43. Clock line, bus, radio frequency line, etc.: The strong radiation signal line is far away from the outgoing signal line of the interface.

Cause: The interference on the strong radiation signal line shall not be coupled to the outgoing signal line and radiate outward.

44. Sensitive signal lines, such as reset signal lines, chip selection signal lines, system control signals, are far away from interface outgoing signal lines.

Cause: External interference is often brought in by the outgoing signal line of the interface, which will lead to system misoperation when coupled to the sensitive signal line.

45. In the single panel and double-sided panel, the routing of the filter capacitor shall be filtered by the filter capacitor first, and then to the device pin.

Cause: The power supply voltage is filtered before supplying power to the IC, and the noise fed back to the power supply by the IC is filtered by the capacitor.

46. In the single panel or double sided panel, if the power line runs very long, the decoupling capacitance should be added to the ground every 3000mil, and the capacitance value is 10uF+1000pF.

Cause: Filter the high-frequency noise on the power line.

47. The grounding wire and power supply wire of the filter capacitor should be as thick and short as possible.

Cause: The equivalent series inductance will reduce the resonant frequency of the capacitor and weaken its high-frequency filtering effect. Circuit board design and circuit board processing manufacturers explain high-speed PCB design rules summary and cause analysis.