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Analysis of PCB Layering
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Analysis of PCB Layering

Analysis of PCB Layering
There are many ways to solve the problem of electromagnetic interference Modern EMI suppression methods include: using EMI suppression coating, selecting appropriate EMI suppression components, and electromagnetic interference simulation design Starting from the most basic PCB PCB layout, this paper discusses the role of PCB stack in controlling EMI radiation and design technology
Power busbar
Proper placement of capacitors of appropriate capacity near the power supply pins of integrated circuits can make the output voltage of integrated circuits jump quickly. However, this is not the end of the problem. Due to the limited frequency response of the capacitor, the capacitor cannot generate the harmonic power required to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop on the inductance of the decoupling path. These transient voltages are the main common mode EMI interference sources. How should we solve these problems?
As far as the integrated circuit on our circuit board is concerned, the power layer around the integrated circuit can be regarded as an excellent high-frequency capacitor, which can collect part of the energy leaked by the discrete capacitor and provide high-frequency energy for clean output. In addition, the inductance of the good power layer should be small, and the transient signal synthesized by the inductor is also small, so as to reduce common mode electromagnetic interference.
Of course, the connection between the power layer and the IC power supply pin must be as short as possible, because the rising edge of the digital signal is faster and faster, it is better to directly connect to the bonding pad where the IC power supply pin is located. This needs to be discussed separately.
To control common mode EMI, the power plane must be decoupled and have a sufficiently low inductance. The power plane must be a pair of well-designed power planes. Some people may ask, how good is it? The answer to this question depends on the layers of power supply, the data between layers and the operating frequency (i.e., the function of IC rise time). Generally, the spacing between power layers is 6mil, the intermediate layer is FR4 data, and the equivalent capacitance of power layers per square inch is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.
Circuit board

pcb board

There are not many devices with a rise time of 100 to 300 ps, but according to the current development speed of integrated circuits, devices with a rise time of 100 to 300 ps will account for a large proportion. For circuits with rise times of 100 to 300 ps, 3 mil layer spacing will no longer be suitable for most applications. At that time, it was necessary to use layered technology with layer spacing less than 1 mil and replace FR4 dielectric material with high dielectric constant data. Today, ceramics and ceramic plastics can meet the design requirements of 100 to 300 ps rise time circuits.
Although new materials and methods may be used in the future, for today's common 1 to 3 ns rise time circuit, 3 to 6 6mil layer spacing and FR4 dielectric data, it is usually sufficient to handle high-end harmonics and make the transient signal low enough, that is, common mode electromagnetic interference can be reduced to a very low level This printed circuit board example of layered stacking design given in this paper will assume a layer spacing of 3 to 6 mils
Electromagnetic mask
From the point of view of signal tracking, a good layering strategy should be to place all signal tracking on one or more layers, which are adjacent to the power layer or ground layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground layer, and the distance between the power layer and the ground layer should be as small as possible. This is what we call a "tiered" strategy.
PCB PCB stacking
What stacking strategies help mask and suppress EMI? The following layered superposition scheme assumes that the power supply current flows on a single layer and that a single voltage or multiple voltages are distributed in different parts of the same layer. The case of multiple power layers will be discussed later.
4-layer plate
There are several potential problems in the design of 4-ply panels. First of all, the traditional four layer plate with a thickness of 62 mils, even if the signal layer is in the outer layer and the power layer and the grounding layer are in the inner layer, the distance between the power layer and the grounding layer is still too large.
If the cost requirement is the first, you can consider the following two traditional 4-layer board alternatives. These two solutions can improve EMI suppression efficiency, but they are only applicable to applications where the density of components on board is low enough and there is enough area around the components (to place the required power copper layer).
The first is the preferred solution The outer layer of PCB is ground layer, and the middle two layers are signal/power layers The power supply on the signal layer adopts wide wire wiring, which can reduce the path impedance of the power supply current, and the impedance of the signal microstrip path is also very low From the perspective of EMI control, this is the best available 4-layer PCB structure In the second scheme, the outer layer uses power and ground, and the middle two layers use signals Compared with the traditional 4-layer plate, the improvement is small, and the interlayer impedance is the same as that of the traditional 4-layer plate
If the trace impedance is to be controlled, the above superposition scheme must be very careful to arrange the trace under the power supply and grounding copper island. In addition, the copper islands on the power supply or ground plane should be interconnected as much as possible to ensure DC and low-frequency connections.

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