Read and understand the causes and manifestations of packaging defects and failures in PCBA processing
Electronic devices are a very complex system, and the defects and failures in the packaging process are also very complex. Therefore, the study of packaging defects and failures requires a systematIC understanding of the packaging process, so as to analyze the causes of defects from multiple perspectives.
1. Research methodology of packaging defects and failures
The failure mechanism of packaging can be divided into two categories: overstress and wear. Overstress failure is usually instantaneous and disastrous; Wear failure is a long-term cumulative damage, which is often first expressed as performance degradation, and then device failure. Failure load types can be divided into mechanical, thermal, electrical, radiation and chEMIcal loads.
There are many factors affecting packaging defects and failures, including material composition and properties, packaging design, environmental conditions and process parameters. Determine the influencing factors and the basic premise to prevent packaging defects and failures. The influencing factors can be determined by experiment or SIMulation, generally using physical model method and numerical parameter method. For more complex defects and failure mechanisms, the trial and error method is often used to determine the key influencing factors, but this method requires longer test time and equipment correction, which is inefficient and costly.
In the process of analyzing the failure mechanism, it is a common method in the industry to use fishbone diagram (cause and effect diagram) to show the influencing factors. Fishbone diagram can explain the relationship between complex causes and influencing factors and packaging defects, and can also distinguish multiple causes and classify them. In production and application, there is a kind of fishbone diagram calLED 6Ms, which analyzes the influencing factors from six dimensions: machine, method, material, measurement, manpower and natural force.
2. Type of load causing failure
The load types of packaging can be divided into mechanical, thermal, electrical, radiation and chemical loads.
Classification of failure mechanisms
Mechanical load: including physical shock, vibration, stress (such as shrinkage stress) and inertial force (such as the huge acceleration of spaceship) imposed by filled particles on silicon chip. The response of materials to these loads may be manifested as elastic deformation, plastic deformation, warping, brittle or flexible fracture, interface delamination, fatigue crack generation and propagation, creep and creep cracking, etc.
Thermal load: including high temperature during curing of chip adhesive, pre heating before wire bonding, molding process, post curing, reprocessing of adjacent components, immersion welding, gas phase welding and reflow welding, etc. The external thermal load will change the size of materials due to thermal expansion, and also change the physical properties such as creep rate. In case of thermal expansion coefficient miSMAtch (CTE mismatch), local stress will be caused, which will eventually lead to package structure failure. Excessive thermal load may even cause combustion of flammable materials in the device.
Electric load: including current fluctuation, electrostatic discharge, over-voltage stress, etc. caused by sudden electric shock, voltage instability or sudden oscillation during current transmission (such as poor grounding). These external electrical loads may cause dielectric breakdown, voltage surface breakdown, heat loss of electrical energy or electromigration. It may also increase electrolytic corrosion, dendrite crystal growth, cause leakage current, heat induced degradation, etc.
Chemical load: including corrosion, oxidation and ion surface dendrite growth caused by chemical use environment. Because moisture can penetrate through the plastic packaging materials, moisture is the main problem affecting plastic packaging devices in humid environments. The moisture absorbed by the plastic packaging material can extract the catalyst residues from the plastic packaging material, forming by-products that enter the metal base, semiconductor materials and various interfaces for chip bonding, causing device performance degradation or even failure.
For example, the flux left on the device after assembly will migrate to the chip surface through the plastic package. In high-frequency circuits, subtle changes in dielectric properties (such as changes in dielectric constant and dissipation factor after moisture absorption) are critical. In high voltage converters and other devices, the change of the breakdown voltage of the package is very important. In addition, some epoxy polyamides and polyurethanes can also cause degradation (sometimes referred to as "reversion") if they are exposed to high temperature and humidity for a long time. Accelerated test is usually used to identify whether the plastic packaging materials are prone to such failure.
It should be noted that when different types of loads are applied, various failure mechanisms may interact on the plastIC encapsulated devices at the same time. For example, thermal load will cause thermal expansion coefficient mismatch between adjacent materials in the package structure, resulting in mechanical failure. Other interactions include stress assisted corrosion, stress corrosion cracking, field induced metal migration, passivation layer and electrolyte layer cracking, package cracking caused by damp and heat, and chemical reaction acceleration caused by temperature, etc. In these cases, the combined effects of failure mechanisms are not necessarily equal to the sum of individual effects.
3. Classification of packaging defects
Packaging defects mainly include lead deformation, base offset, warpage, chip breakage, delamination, voids, uneven packaging, burrs, foreign particles and incomplete curing.
3.1 Lead wire deformation
Lead wire deformation usually refers to the lead wire displacement or deformation caused by the flow of plastic packaging material, which is usually expressed by the ratio x/L between the maximum lateral displacement x of the lead wire and the length L of the lead wire. Bent leads may cause electrical short circuits (especially in high-density I/O device packages). Sometimes, the stress generated by bending will cause the bond point to crack or the bond strength to decrease.
The factors that affect wire bonding include package design, wire layout, wire material and size, molded plastic properties, wire bonding process and packaging process. Lead wire parameters affecting lead wire bending include lead wire diameter, lead wire length, lead wire breaking load, lead wire density, etc.
3.2 Substructure offset
Base offset refers to the deformation and offset of the carrier (chip base) supporting the chip.
The factors that affect the base offset include the fluidity of the plastic package, the assembly design of the lead frame, and the material properties of the plastic package and the lead frame. Due to the thin lead frame, package devices such as Thin Small Size Package (TSOP) and Thin Square Flat Package (TQFP) are prone to base offset and pin deformation.
Warpage refers to the bending and deformation of packaged devices outside the plane. Warpage caused by plastic packaging process will lead to a series of reliability problems such as delamination and chip cracking.
Warpage can also lead to a series of manufacturing problems. For example, in plastic ball grid array (PBGA) devices, warpage can lead to poor coplanarity of solder balls, resulting in mounting problems during reflow soldering of devices assembled to printed circuit boards.
Warpage modes include concave, convex and combined modes. In semiconductor companies, the concave is sometimes called "smiling face" and the convex is called "crying face". The causes of warpage mainly include CTE mismatch and curing/compression shrinkage. The latter did not receive much attention at the beginning. Through in-depth research, it was found that the chemical shrinkage of molding compound also played an important role in the warpage of IC devices, especially on the packaging devices with different thicknesses on the upper and lower sides of the chip.
In the process of curing and post curing, the plastic packaging material will undergo chemical shrinkage at high curing temperature, which is called "thermochemical shrinkage". The chemical shrinkage in the curing process can be reduced by increasing the glass transition temperature and decreasing the thermal expansion coefficient near Tg.
The factors that cause warpage also include the composition of the plastic package, the moisture of the molding compound, the geometry of the package, etc. By controlling the plastic packaging materials and components, process parameters, packaging structure and pre packaging environment, packaging warpage can be minimized. In some cases, warpage can be compensated by packaging the back of the electronIC components. For example, the external connections of large ceramic circuit boards or multilayer boards are located on the same side, and they can be back packaged to reduce warpage.
3.4 Chip breakage
The stress generated in the packaging process will lead to chip breakage. The packaging process usually aggravates the micro cracks formed in the previous assembly process. Wafer or chip thinning, back grinding and chip bonding are all steps that may lead to chip crack initiation.
Broken, mechanically failed chips do not necessarily lead to electrical failure. Whether the chip breakage will lead to the instantaneous electrical failure of the device depends on the growth path of the crack. For example, if cracks appear on the back of the chip, they may not affect any sensitive structures.
Because silicon wafers are thin and brittle, wafer level packages are more prone to chip breakage. Therefore, the process parameters such as clamping pressure and forming conversion pressure in the transfer molding process must be strictly controlled to prevent chip breakage. Chip breakage is easy to occur in 3D stack packaging due to the stacking process. The design factors that affect chip breakage in 3D packaging include chip stack structure, substrate thickness, molded volume and die sleeve thickness.
Delamination or poor adhesion refers to the separation between the interface of the plastic sealant and its adjacent materials. The delamination position may occur in any area of the plastic encapsulated microelectronic device; It may also occur in the packaging process, post packaging manufacturing stage or device use stage.
Poor bonding interface caused by packaging process is the main factor causing delamination. Voids in the interface, surface contamination during encapsulation, and incomplete curing can all lead to poor bonding. Other influencing factors include shrinkage stress and warpage during curing and cooling. During the cooling process, the mismatch of CTE between the encapsulant and adjacent materials will also lead to thermal mechanical stress, resulting in delamination.
In the packaging process, bubbles are embedded in the epoxy material to form cavities, which can occur at any stage of the packaging process, including transfer molding, filling, filling and printing of plastic packaging materials in the air environment. Cavities can be reduced by minimizing the amount of air, such as emptying or vacuuming. It is reported that the vacuum pressure range used is 1~300 Torr (760 Torr for one atmOSPhere).
According to the simulation analysis of mold filling, it is the contact between the front edge of the bottom melt and the chip that hinders the fluidity. Part of the melt front flows upward and fills the top of the half mold through the large opening area around the chip. The newly formed melt front and the adsorbed melt front enter the top area of the half mold to form bubbles.
3.7 Uneven packaging
Uneven plastic package thickness will lead to warping and delamination. Traditional packaging technologies, such as transfer molding, pressure molding and injection molding, are not easy to produce packaging defects with uneven thickness. Wafer level packaging is particularly prone to lead to uneven plastic packaging thickness due to its process characteristics.
In order to ensure a uniform thickness of the plastic packaging layer, the wafer carrier should be fixed so that its gradient is minimum for the convenience of scraper installation. In addition, scraper position control is required to ensure that the scraper pressure is stable, so as to obtain a uniform plastic seal layer thickness.
Before hardening, when the filler particles gather in the local area of the plastic package and form uneven distribution, it will lead to heterogeneous or uneven material composition. The insufficient mixing of plastic packaging materials will lead to the occurrence of heterogeneous phenomena in the packaging and potting process.
Burr refers to molding compound deposited on device pins through parting line in plastic packaging process.
Insufficient clamping pressure is the main cause of burrs. If the die residue on the pin is not removed in time, various problems will occur in the assembly stage. For example, the bonding or adhesion is insufficient in the next packaging stage. Resin leakage is a relatively sparse form of burr.
3.9 Foreign particles
In the packaging process, if the packaging materials are exposed to the polluted environment, equipment or materials, foreign particles will diffuse in the packaging and gather on the metal parts in the packaging (such as IC chips and lead bonding points), resulting in corrosion and other subsequent reliability problems.
3.10 Incomplete curing
Insufficient curing time or low curing temperature will lead to incomplete curing. In addition, in the pouring of two kinds of encapsulation materials, the slight deviation of the mixing proportion will lead to incomplete curing. In order to maximize the characteristics of packaging materials, it is necessary to ensure that the packaging materials are fully cured. In many packaging methods, post curing method is allowed to ensure complete curing of packaging materials. And pay attention to ensure the accurate proportion of packaging materials.
These are the causes and manifestations of packaging defects and failures in PCBA processing explained by the circuit board design and the circuit board manufacturer