When designing a high-performance data acquisition system, diligent engineers carefully select a high-precision ADC and other components needed to simulate the front-end regulation circuit. After several weeks of design work, performing simulations and optimizing circuit schematics, designers quickly put the board layout and wiring together to meet deadlines. A week later, the first prototype circuit board was tested. Unexpectedly, the performance of the board is not as expected.
Has this ever happened to you?
Optimal PCB layout is important for the ADC to achieve the desired performance. When designing a circuit that includes mixed-signal devices, you should always start with a good grounding arrangement and divide the design into analog, digital, and power components using optimal component placement and signal routing.
The reference path is the most critical in the ADC layout because all conversions are a function of the reference voltage. In the traditional successive approximation register (SAR) ADC architecture, the reference path is also the most sensitive because the reference pin has a dynamic load to the reference source.
Since the reference voltage is sampled several times during each conversion, a high current transient occurs at this terminal, where the ADC internal capacitor array is turned on and charged at this position. The reference voltage must remain stable for each conversion clock cycle and stabilize to the desired N bit resolution, otherwise linear errors and code loss errors will occur.
Figure 1 shows the current transients during the conversion phase on a typical 12-bit SAR ADC reference terminal.
Bit current transient on the reference pin of the SAR ADC
Because of these dynamic currents, a high quality bypass capacitor (CREF) is required to decouple the reference pin. This bypass capacitor is used as a charge memory to provide instantaneous charging during these high-frequency transient currents. You should place the reference bypass capacitors as close to the reference pin as possible and connect them together using shorter, low-inductance connections.
Figure 2 shows an example of board layout wiring for the ADS7851, a 14-bit dual ADC with two independent voltage references.
Example of dual ADC layout wiring with two independent internal voltage references
In this example of a four-layer PCB board, the designers used a solid ground plane located directly below the device, and the board was divided into analog and digital sections to keep sensitive inputs and reference signals away from noise sources. He uses 10μF, X7R class 0805 ceramic capacitors (CREF-x) to bypass the REFOUT-A and REFOUT-B reference outputs for optimal performance and connects them to devices using small 0.1Ω series resistors to maintain overall low impedance and constant impedance at high frequencies. He also used wide trace lines to reduce inductance.
I strongly recommend placing CREF and ADC on the same layer. You should also avoid placing a pilot hole between the reference pin and the bypass capacitor. Each reference ground pin of the ADS7851 has a separate ground connection, while each bypass capacitor has a separate inductive connection to the ground path.
If you are using an ADC that requires an external reference source, you should minimize the inductance in the reference signal path - this path starts from the reference buffer output to the bypass capacitor until the ADC reference input.
Figure 3 shows an example of an 18-bit, SAR, ADC ADS8881 layout cabling using an external reference and buffer. By placing the capacitor within 0.1 inches of the pin and connecting it to a 20-mil-wide trace and multiple 15-mil-sized ground pilot holes, the designer keeps the inductance between the reference capacitor and the REF pin to less than 2nH. I recommend a single, 10uF, X7R class, size 0805 ceramic capacitor with a rated voltage of at least 10V.
The trace length from the reference buffer circuit to the REF pin is kept as short as possible to ensure a fast and stable response.
Proper decoupling of the REF pins is critical to achieving optimal performance. In addition, keeping a low inductance connection in the reference path allows the reference drive circuit to remain stable during conversion, bringing you one step closer to achieving the desired results.