When **PCB wiring**is carried out, it often happens that a thinner line has to be used when routing through an area due to the limited wiring space in the area. After passing through this area, the line will be restored to its original width. Changes in the width of the line will cause impedance changes, so reflection occurs, affecting the signal. So when can we ignore this effect, and when must we consider its effect?

Three factors are associated with this effect: the size of the impedance change, the signal rise time, and the time delay of the signal along the narrow line.

The magnitude of the impedance change is discussed first. **Many circuits** are designed to reflect noise less than 5% of the voltage swing (which is related to the noise budget on the signal). According to the reflection coefficient formula:

ρ= (Z2-z1)/(Z2+Z1) =△Z/(△Z+2Z1) ≤5%

The approximate change rate of impedance can be calculated as follows: △Z/Z1≤10%

As you probably know, the typical impedance on a circuit board is +/-10%, and that's the root cause.

If the impedance change occurs only once, for example, after the line width changes from 8mil to 6mil, and remains 6mil, the impedance change must be less than 10% in order to achieve the noise budget requirement that the noise reflected by the signal at the mutation does not exceed 5% of the voltage swing. This is sometimes difficult to do, as in the case of microstrip lines on FR4 plates, let's calculate. If the line width is 8mil, the thickness between the line and the reference plane is 4mil and the characteristic impedance is 46.5 ohms. After the line width changes to 6mil, the characteristic impedance becomes 54.2 ohm, and the impedance change rate reaches 20%. The amplitude of the reflected signal must exceed the limit. As for how much impact on the signal, also depends on the signal rise time and the signal delay from the driving end to the reflection point. But at the very least it's a potential problem spot. Fortunately, the problem can be solved by impedance matching terminating.

If the impedance changes twice, for example, after the line width changes from 8mil to 6mil, pull out 2cm and then change back to 8mil. Then there will be reflections at both ends of a 2cm long 6mil wide line, once the impedance increases and a positive reflection occurs, then the impedance decreases and a negative reflection occurs. If the time between reflections is short enough, they may cancel each other out, reducing the impact. Assuming the transmission signal is 1V, the first positive reflection has 0.2V reflected, 1.2V continues forward transmission, and the second reflection has -0.2*1.2 = 0.24v reflected back. Assuming that the length of the 6mil line is extremely short and the two reflections occur almost simultaneously, the total reflected voltage is only 0.04V, less than the 5% noise budget requirement. Therefore, whether and how much this reflection affects the signal depends on the time delay at the impedance change and the time the signal rises. Studies and experiments show that as long as the delay at the impedance change is less than 20% of the signal rise time, the reflected signal will not cause problems. If the signal rise time is 1ns, then the delay at the impedance change is less than 0.2ns for 1.2 inches, and the reflection will not be a problem. That is, for this example, the length of the 6mil wide line should not be a problem as long as it is less than 3cm.

When the** PCB wiring** width changes, it should be carefully analyzed according to the actual situation to determine whether it will cause any impact. There are three parameters to be concerned about: how much impedance change, how much signal rise time, and how long the neck part of the line width change. According to the above method roughly estimate, appropriate to set aside a certain amount of margin. If possible, minimize the length of the neck.

It should be pointed out that in the actual **PCB processing**, the parameters cannot be as accurate as in the theory. The theory can provide guidance for our design, but it cannot be copied or dogma. After all, this is a practical science. The estimated value should be properly revised according to the actual situation, and then applied to the design.

5. The tray fixture has been used

If all the above methods are difficult, reflow carrier/template is used to reduce the deformation. The reason why Reflow carrier/template can reduce the bending and warping of the plate is that whether it is hot expansion or cold contraction, It is hoped that the tray can hold the **circuit board** and maintain the size of the garden when the temperature of the circuit board is below the Tg value and begins to harden again.

If a single layer of tray can not reduce the deformation of the circuit board, it is necessary to add a layer of cover, the circuit board with two layers of tray clip up, so that you can greatly reduce the circuit board over the welding furnace deformation problem. But the trays are expensive, and you have to add labor to place and retrieve them.

6. Use the Router instead of the V-Cut

Since V-cuts can damage the structural strength of the board, try not to use V-Cut subboards, or reduce the depth of the V-Cut.