Later, when the whole social production industry developed to a certain extent, many participants often belong to each other, in fact, quite a number of enterprises themselves did not research and development or initiative ability, so, resulting in a lot of products and users of electronic products (circuit board bottom or electronic products as a whole) performance is poor, and the main reason for poor performance is because of impedance problems , because when unqualified chemical tin plating technology is used, the tin plated for PCB board is not really pure tin (or pure metal elemental), but a tin compound (that is, not a metal elemental at all, but a metal compound, oxide or halide, more directly a non-metallic substance) or a mixture of tin compound and tin gold elemental substance. But it's hard to see with the naked eye... .
Because the main circuit of the PCB circuit board is copper foil, in the solder joint of the copper foil is tin layer, and the electronic components is through the solder paste (or solder line) welding in the tin layer above, in fact, the solder paste in the state of melting welding to the electronic components and tin coating between the metal tin (that is, a good conductive metal), so it can be simply pointed out that the electronic components are through the tin The coating is connected with the copper foil at the bottom of the PCB board, so the purity and impedance of the tin coating is the key; Also, but before inserting electronic components, we directly use the instrument to detect impedance, in fact, both ends of the instrument probe (or pen) is also through the first contact with the copper foil surface at the bottom of the PCB board tin coating and copper foil at the bottom of the PCB board to communicate the current. Therefore, tin coating is the key, is the key to affect the impedance and the key to affect the performance of the entire PCB board, is also easy to be ignored.
As we all know, in addition to the metal elemental, its compounds are electrical conductors or even non-conductive (in addition, this is also the key to the existence of distribution capacity or distribution capacity in the line), so the existence of such conductive but non-conductive tin compounds or mixtures in the tin coating, its ready-made resistivity or future oxidation, moisture after the occurrence of electrolytic reaction resistivity and its corresponding impedance Is quite high (enough to affect the level or signal transmission in a digital circuit) and its characteristic impedance is inconsistent. Therefore, it will affect the performance of the circuit board and its complete machine.
Therefore, in terms of the current social production phenomenon, the coating material and performance on the bottom of PCB board is the most important and direct reason affecting the characteristic impedance of PCB board, but because of its change with the coating aging and moisture electrolysis, so the impact of its impedance becomes more recessive and variable, the main reason for its hidden is: The first can not be seen by the naked eye (including its changes), the second can not be always measured, because it has changes with the change of time and environmental humidity, so it is always easy to be ignored.
The simulation of passive channel is divided into pre-layout simulation and post-layout simulation. Please refer to the red and black arrows below to indicate the direction, which all start from PCB import. Pre-layout simulation is in HFSS 3D layout. Each impedance discontinuous structure (goldfinger, through hole, coupling capacitance, interface of pcb and fpc, etc.) is cut out, and then exported to HFSS for local optimization. After optimization, the corresponding structural size parameters are directed to layout engineer for modification of PCB. Here, why not directly optimize 3D layout in HFSS, because 3D layout drawing ability is relatively weak, although some variables can be set parameterized, but far less convenient optimization than in HFSS, so local optimization is recommended to be carried out in HFSS. Simulation of other optical devices and high-speed submounts also needs to be performed in HFSS.
However, I suggest that the post-layout simulation be completed directly in 3D layout. Of course, HFSS can also be used to cope with this work, but it is relatively tedious to guide and export the model again. In 3D layout, after cutting out the net to be analyzed, you can import 3d component. QSFP28 connector, SFP+ connector and SMA connector are common on optical mode. In this way, the simulation of the whole passive path can be carried out. And the use of 3d layout of phi mesh, mesh division can save a little time, after all, layout simulation, the model is relatively large, more than 300,000 grid number is very common.
After the passive simulation performance adjustment, it is necessary to carry out the cascade simulation of the whole TX and RX channel, which belongs to the active simulation. It is necessary to observe the voltage, current waveform, eye diagram and EO/OE response bandwidth of the channel. The following is the overall simulation summary diagram of the DML model emission channel, and there are some details to be carefully handled. Please refer to the caption in the image below.
The above is the overview of optical module PCB and optical device simulation. There are not many things to simulate, but there are also many places to be carefully handled. The above content is just a summary of my personal experience, please forgive the mistakes, thank you!
The following article is from ANSYS veteran, by Liu Xing 925