This is mainly for high voltage driver chips with built-in power modulators. If the current consumed by the chip is 2mA, 300V voltage is applied to the chip, and the power consumption of the chip is 0.6W, of course, it will cause the heat of the chip. The large current of the driver chip comes from the consumption of the driving power MOS tube. The simple calculation formula is I=cvf.
Considering the resistance benefit of charging, the actual I=2cvf, where c is the cgs capacitance of the power MOS tube and v is the gate voltage when the power tube is switched on. Therefore, in order to reduce the power consumption of the chip, try to reduce c, v and f. If c, v, f cannot be changed, then please find a way to distribute the power of the chip to the off-chip device. Be careful not to introduce additional power consumption. Another simple point is to consider the best heat dissipation.
Power tube heating
The power consumption of power tube is divided into two parts, switching loss and on-off loss. Note that most occasions, especially LED mains drive applications, switch damage is far greater than the on-off loss. The switching loss is related to the cgd and cgs of the power tube as well as the driving capacity and working frequency of the chip, so the heating of the power tube can be solved from the following aspects:
01. MOS power tube can not be selected unilaterally according to the size of the on-off resistance, because the smaller the internal resistance, the larger the capacitance of cgs and cgd.
For example, cgs for 1N60 is about 250pF, 2N60 cgs is about 350pF, 5N60 cgs is about 1200pF, the difference is too big, when choosing a power tube, enough is enough.
02, the rest is frequency and chip drive capability, here only talk about the effect of frequency. Frequency is also proportional to conduction loss, so when the power tube heating, * to think about whether the frequency selection is a little high. Find a way to lower the frequency!
However, it should be noted that when the frequency decreases, in order to obtain the same load capacity, the peak current must be increased or the inductance must also be increased, which may lead to the inductance entering the saturation region. If the inductance saturation current is large enough, you can consider changing CCM (continuous current mode) to DCM (discontinuous current mode), so you need to add a load capacitor.
Operating frequency drops
This is also a common phenomenon in the process of debugging, frequency reduction is mainly caused by two aspects. The input voltage and load voltage ratio is small, the system interference is large. For the former, be careful not to set the load voltage too high, although the load voltage is high, the efficiency will be high. For the latter, try the following:
1. Set the small current lower;
2. Clean wiring, especially the critical path of sense;
3. Select a small inductance or the inductance of a closed magnetic circuit;
4. Add RC low-pass filtering. The effect is a little bad. The consistency of C is not good and the deviation is a little large, but it should be enough for lighting.
There is no upside to downscaling anyway, only downside, so be sure to fix it.
Choice of inductor or transformer
With the same drive circuit, the inductance produced by a has no problem, and the inductance current produced by b becomes smaller. In this case, look at the inductive current waveform. Some do not notice this phenomenon, directly adjust the sense resistance or working frequency to reach the required current, which may seriously affect the service life of LED.
Therefore, before the design, reasonable calculation is perfect, if the theoretical calculation parameters and debugging parameters are a little far away, to consider whether the frequency reduction and transformer saturation. When the transformer is saturated, L will become smaller, resulting in a sharp rise in the peak current increment caused by transmission delay, so the peak current of LED will also increase. If the average current stays the same, you can only watch the light fade.
LED current size
We all know that if the LED ripple is too large, the LED life will be affected, how much impact, have not seen which said. I have asked the LED factory about this data before, and they said it is acceptable within 30%, but it has not been verified later. I suggest keeping it as small as possible. If the heat dissipation is not solved well, the LED must be derated. I also hope to have a specific index, otherwise it will affect the promotion of LED.
1. Brief introduction of structure and working principle of MOS transistor
It is more or less known that the main function of a transistor in a digital circuit is an electronic switch, which is turned on or off by a voltage or a current. There are roughly two kinds of transistors: One is bipolar junction transistor and the other is metal-oxide-semiconductor field-effect transistor (MOSFET or MOS). metal-oxide-semiconductor field effect transistor). Here we mainly talk about MOS, BJT in the current digital IC design is not the mainstream technology.
①MOS transistors are divided into PMOS and NMOS, which kind of MOS depends on the substrate and doping concentration. As for how it is formed, it is too complicated to explain in a few words, so let's skip it and look directly at their cross section diagram and briefly explain how they work (NMOS are taken as examples below).
The cross-sectional structure of the NMOS transistor is shown as follows:
IC design: CMOS devices and their circuits
The substrate is a silicon substrate (where the Body Si is), the top is a conductive gate, and the middle is an insulating layer composed of silica. In the past, the gate * was made of metal, so it was called metal-oxide-semiconductor. Now the gate * uses poly. In the MOS structure, a capacitor is formed by silica between a metal (polysilicon) and a semiconductor substrate.
Well, it doesn't matter if you don't understand the above paragraph, but remember that in the above NMOS transistor, the substrate is P-type, and there are two N-type doping regions on the substrate called Source and Drain. (You can define the left side as the drain and the right side as the source.) Since the device is symmetrical at this time, S and D are not really determined until the power supply and ground are connected), the upper middle is called Gate * (Gate), which is the three electrodes of NMOS (actually MOS is a 4-terminal device, and its substrate is also a terminal). Here's how they work.