In the power circuit design, electromagnetic interference is one of the key factors affecting the product performance. At present, for engineers, there are many ways to solve the problem of EMI. The commonly used methods to suppress EMI include: EMI suppression coating, EMI SIMulation design, and the selection of appropriate EMI suppression parts. This article will start with PCB, and introduce the function and design skills of PCB layered stacking in controlling EMI radiation.
How to Solve EMI to Improve the Performance of multilayer PCB Products
If a capacitor with appropriate capacity is reasonably placed near the power supply pin of the IC, the jump of the IC output voltage can be faster. However, the problem does not stop there. Due to the limited frequency response of the capacitor, it is impossible for the capacitor to generate the harmonic power required to drive the IC output cleanly in the full frequency band. In addition, the transient voltage formed on the power bus will form a voltage drop at both ends of the inductance in the decoupling path, and these transient voltages are the main common mode EMI interference sources. How should we solve these problems?
As far as the IC on our circuit board is concerned, the power supply layer around the IC can be regarded as a good high-frequency capacitor, which can collect the energy leaked by the discrete capacitors that provide high-frequency energy for clean output. In addition, the inductance of the excellent power supply layer is SMAll, so the transient signal synthesized by the inductance is small, thereby reducing the common mode EMI.
Of course, the connection from the power supply layer to the IC power supply pin must be as short as possible, because the rising edge of the digital signal is getting faster and faster. It is better to connect it directly to the bonding pad where the IC power supply pin is located. This should be discussed separately.
In order to control the common mode EMI, the power supply layer should help decoupling and have a sufficiently low inductance. This power supply layer must be a pair of well-designed power supply layers. Some people may ask, how good is it? The answer to the question depends on the layering of the power supply, the materials between layers, and the operating frequency (that is, the function of IC rise time). Generally, the spacing between power layers is 6mil, and the interlayer is made of FR4 material, so the equivalent capacitance of each square inch of power layer is about 75pF. Obviously, the smaller the layer spacing, the larger the capacitance.
There are not many devices with a rise time of 100 to 300 ps, but according to the current development speed of IC, devices with a rise time of 100 to 300 ps will occupy a high proportion. For circuits with 100 to 300 ps rise time, 3 mil layer spacing is no longer appropriate for most applications. At that time, it was necessary to adopt the layering technology with layer spacing less than 1mil, and replace the FR4 dielectric material with a material with high dielectric constant. Now, ceramics and ceramic plastics can meet the design requirements of 100 to 300 ps rise time circuits.
Although new materials and methods may be used in the future, common mode EMI can be reduced to a very low level for common 1 to 3 ns rise time circuits, 3 to 6 mil layer spacing, and FR4 dielectric materials, which are usually sufficient to handle high-end harmonics and make transient signals low enough. The PCB layered stacking design example given in this paper will assume that the layer spacing is 3 to 6 mil.
From the point of view of signal routing, a good layering strategy should be to place all signal routing on one or several layers, which are close to the power layer or grounding layer. For power supply, a good layering strategy should be that the power layer is adjacent to the ground plane, and the distance between the power layer and the ground plane should be as small as possible. This is what we call "layering" strategy.
What stacking strategies help shield and suppress EMI? The following layered stacking scheme assumes that the power supply current flows on a single layer and that single or multiple voltages are distributed in different parts of the same layer. The case of multiple power layers will be discussed later.
There are several potential problems in the design of 4-layer plates. First of all, for the traditional four layer plate with a thickness of 62mil, even if the signal layer is in the outer layer and the power and ground layers are in the inner layer, the distance between the power and ground layers is still too large.
If the cost requirement is the first, the following two alternatives to the traditional 4-layer board can be considered. Both schemes can improve the performance of EMI suppression, but they are only applicable to the situations where the density of components on the board is low enough and there is enough area around the components (to place the required power supply copper clad layer).
The first is the preferred solution. The outer layer of PCB is the stratum, and the middle two layers are the signal/power layer. The power supply on the signal layer is routed with a wide wire, which makes the path impedance of the power supply current low and the impedance of the signal microstrip path low. From the perspective of EMI control, this is the best 4-layer PCB structure available; The outer layer of the second scheme uses power and ground, and the middle two layers use signals. Compared with the traditional 4-layer board, the improvement of this scheme is smaller, and the interlayer impedance is as poor as that of the traditional 4-layer board.
If the routing impedance is to be controlLED, the above stacking schemes should be very careful to arrange the routing under the power supply and grounding copper island; In addition, the copper islands on the power supply or stratum shall be interconnected as much as possible to ensure the connectivity of DC and low-frequency.
If the component density on the 4-layer board is relatively large, it is better to use the 6-layer board. However, some stacking schemes in the 6-layer Board Design do not shield electromagnetic fields well enough, and have little effect on reducing the transient signal of the power bus. In the first example, the power supply and ground are placed on the second and fifth layers respectively. Because of the high copper clad impedance of the power supply, it is very unfavorable to control the common mode EMI radiation. However, from the point of view of signal impedance control, this method is very correct.