The blind hole is located on the top and bottom surfaces of the **printed circuit board**, and has a certain depth. It is used to connect the surface line and the lower inner line. The depth of the hole usually does not exceed a certain ratio (aperture). Embedded hole refers to the connection hole located in the inner layer of the printed circuit board, whICh will not extend to the surface of the printed circuit board. The above two types of holes are located in the inner layer of the circuit board. Before lamination, the through hole forming process is used to complete the hole. During the hole forming process, several inner layers may be overlapped. The third is calLED through hole, which passes through the whole circuit board and can be used for internal interconnection or as the installation positioning hole of components. Because the through-hole is easier to realize in technology and lower in cost, it is used in most printed circuit boards instead of the other two kinds of through-hole. The following vias, unless otherwise specified, are considered as through-hole.

1、 From the design point of view, a via is mainly composed of two parts: one is the drill hole in the middle, and the other is the pad area around the drill hole. The size of these two parts determines the size of the vias. Obviously, when designing high-speed and high-density **PCBs**, designers always hope that the SMAller the vias are, the better, so that more wiring space can be left on the board. In addition, the smaller the vias are, the smaller their parasitic capacitance is, which is more suitable for high-speed circuits. However, the reduction of hole size also brings about an increase in cost, and the size of vias cannot be reduced without limitation. It is limited by **PCB drilling**, electroplating and other technologies: the smaller the hole, the longer it takes to drill, and the easier it is to deviate from the center; And when the depth of the hole exceeds 6 times of the drilling diameter, it is impossible to ensure that the hole wall can be uniformly copper plated. For example, the normal thickness (through-hole depth) of a 6-layer PCB is about 50Mil, so the minimum drilling diameter provided by the PCB manufacturer can only reach 8Mil.

2、 Parasitic capacitance of via The via itself has parasitic capacitance to ground. If it is known that the diameter of the isolation hole of the via on the floor is D2, the diameter of the via pad is D1, the thickness of the PCB is T, and the dielectric constant of the board substrate is ε, Then the parasitic capacitance of the via is approximately C=1.41 ε The parasitic capacitance of TD1/(D2-D1) via will mainly affect the circuit by prolonging the signal rise time and reducing the circuit speed. For example, for a PCB with a thickness of 50Mil, if a via with an inner diameter of 10Mil and a pad diameter of 20Mil is used and the distance between the pad and the ground copper area is 32Mil, we can approximately calculate the parasitic capacitance of the via through the above formula: C=1.41x4.4 x 0.050 x 0.020/(0.032-0.020)=0.517pF, and the rise time change caused by this part of capacitance is T10-90=2.2C (Z0/2)=2.2 x 0.517x (55/2)=31.28ps. It can be seen from these values that, although the effect of the rise delay caused by the parasitic capacitance of a single via is not obvious, the designer should carefully consider if the via is used for switching between layers for many times in routing.

3、 Parasitic inductance of vias is the same. Parasitic capacitance also exists in vias. In **PCB design** of high-speed digital circuits, the harm of parasitic inductance of vias is often greater than the influence of parasitic capacitance. Its parasitic series inductance will weaken the contribution of bypass capacitor and the filtering effectiveness of the whole power supply system. We can use the following formula to SIMply calculate the approximate parasitic inductance of a via: L=5.08h [ln (4h/d)+1], where L is the inductance of the via, h is the length of the via, and d is the diameter of the central borehole. It can be seen from the formula that the diameter of the via has little influence on the inductance, while the length of the via has the greatest influence on the inductance. Using the above example, we can calculate the inductance of the via as: L=5.08x0.050 [ln (4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, the equivalent impedance is XL=π L/T10-90=3.19 Ω. Such impedance cannot be ignored when there is high-frequency current passing through. In particular, the bypass capacitor needs to pass through two vias when connecting the power layer and the stratum, so the parasitic inductance of the vias will be multiplied.

4、 Through the above analysis of the parasitic characteristics of vias in high-speed PCB design, we can see that in high-Speed PCB design, seEMIngly simple vias often bring great negative effects to circuit design. In order to reduce the adverse effects caused by the parasitic effect of vias, the following measures can be taken in the design:

1. Considering the cost and signal quality, the reasonable size of vias is selected. For example, for the 6-10 layer memory module PCB design, it is better to select 10/20Mil (drilling/pad) vias. For some high-density small size boards, you can also try to use 8/18Mil vias. Under the current technical conditions, it is difficult to use smaller vias. For the via of power supply or ground wire, the larger size can be considered to reduce the impedance.

2. From the two formulas discussed above, it can be concluded that the use of thinner PCB is beneficial to reduce the two parasitic parameters of vias.

3. The signal wiring on the PCB shall not change layers as much as possible, that is to say, unnecessary vias shall not be used as much as possible.

4. The pins of power supply and ground shall be punched nearby. The shorter the lead between the via and pin, the better, because they will lead to an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance.

5. Place some grounded vias near the vias for signal layer change, so as to provide the nearest circuit for the signal. You can even place a large number of redundant grounding vias on the PCB. Of course, PCB design needs to be flexible. The vias model discussed above is the case that each layer has pads. Sometimes, we can reduce or even remove pads from some layers. Especially when the vias density is very large, it may cause a break slot of the partition circuit to be formed in the copper layer. To solve this problem, we can also consider reducing the size of the **PCB pad** with vias on the copper layer in addition to moving the vias position.