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Overview of Signal Integrity Design for High Speed PCB
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Overview of Signal Integrity Design for High Speed PCB

Signal integrity design issues to be considered in gigabit data transmission, and methods to solve these issues using PCB design tools are introduced, such as skin effect and dielectrIC loss, effects of vias and connectors, differential signal and wiring considerations, power distribution and EMI control.

With the rapid development of communication and computer technology, high-speed PCB design has entered the gigabit field. The application of new high-speed devices makes it possible to transmit such a high speed over a long distance on the backplane and single board. At the same time, the problems of signal integrity (SI), power supply integrity and electromagnetic compatibility in PCB design have become more prominent.


Signal integrity refers to the quality of signal transmission on the signal line. The main problems include reflection, oscillation, timing, ground bounce and crosstalk. Poor signal integrity is not caused by a single factor, but by multiple factors in board level design. In the PCB design of gigabit devices, a good signal integrity design requires engineers to fully consider PCB devices, transmission line interconnection schemes, power distribution and EMC issues.

EDA tools for high-Speed PCB design have developed from SIMple simulation verification to combination of design and verification, helping designers set rules in early design to avoid errors rather than finding problems in late design. With the increasing data rate and complexity of design, high-speed PCB system analysis tools become more necessary. These tools include timing analysis, signal integrity analysis, design space parameter scanning analysis, EMC design, power system stability analysis, etc. Here we will focus on some issues that should be considered in signal integrity analysis in the design of gigabit PCB.

High Speed PCB devices and device models

Although the supplier of gigabit sending and receiving components will provide the design information about the chip, there is a process for the component supplier to understand the signal integrity of the new component. In this way, the guidance given by the component supplier may not be mature. In addition, the design constraints given by the component supplier are usually very strict, which will be very difficult for the design engineer to meet all the design rules. Therefore, signal integrity engineers need to use simulation analysis tools to analyze the constraint rules and actual design of suppliers, investigate and optimize component selection, topology, matching scheme, and values of matching components, and finally develop PCB layout and wiring rules to ensure signal integrity. Therefore, the accurate simulation and analysis of gigabit signals has become very important, and the role of device models in signal integrity analysis has been paid more and more attention.

Component models usually include IBIS model and SPIce model. Because board level simulation only cares about the signal response from the output pin to the input pin through the interconnection system, and IC manufacturers do not want to leak the detaiLED circuit information inside the device, and the simulation time of transistor level Spice model is usually unbearable, IBIS model is gradually accepted by more and more device manufacturers and signal integrity engineers in the field of high-speed PCB design.

For the simulation of gigabit device PCB system, engineers often question the accuracy of IBIS model. When the device operates in the saturation and cut-off region of the transistor, IBIS model lacks sufficient detailed information to describe it. In the nonlinear region of the transient response, the simulation results using IBIS model cannot produce accurate response information as transistor level model does. However, for ECL type devices, IBIS model can be obtained which is very consistent with the simulation results of transistor level model. The reason is simple. ECL driver works in the linear region of the transistor, and the output waveform is closer to the ideal waveform. According to IBIS standard, a more accurate IBIS model can be obtained.

With the increase of data transmission rate, differential devices based on ECL technology have been greatly developed. LVDS standard and CML make gigabit signal transmission possible. From the above discussion, we can see that IBIS standard is still applicable to the design of gigabit systems due to the circuit structure and the corresponding differential technology application. Some published articles on the application of IBIS model in 2.5Gbps LVDS and CML design also prove this point.

Since IBIS model is not suitable for describing active circuits, it is not suitable for many Gbps devices with pre emphasis circuits for loss compensation. Therefore, in the design of gigabit system, IBIS model can only work effectively under the following conditions:

1. The differential device works in the amplification area (linear V-I curve)

2. The device has no active pre emphasis circuit

3. The device has a pre emphasis circuit but is not started (starting the pre emphasis function in a short interconnected system may lead to worse results)

4. The device has a passive pre emphasis circuit, but the PCB circuit can be separated from the bare chip of the device.

When the data rate is 10Gbps or above, the output waveform is more like a sine wave, and the Spice model is more applicable.

Loss effect

When the signal frequency increases, the attenuation on the transmission line cannot be ignored. At this time, the loss caused by the equivalent resistance of the conductor in series and the equivalent conductance of the dielectric in parallel should be considered, and the lossy transmission line model should be used for analysis.

The equivalent model of the lossy transmission line is shown in Figure 1. It can be seen from the figure that the equivalent series resistance R and the equivalent parallel conductance G represent the loss. The equivalent serial resistance R is the resistance caused by the DC resistance and skin effect. The DC resistance is the resistance of the conductor itself, which is determined by the physical structure of the conductor and the resistivity of the conductor. When the frequency increases, the skin effect starts to work. The skin effect is a phenomenon that when the high-frequency signal passes through the conductor, the signal current in the conductor concentrates on the surface of the conductor. In the conductor interior, the current density of the signal along the conductor section decreases exponentially, and the depth when the current density decreases to 1/e is called skin depth. The higher the frequency is, the SMAller the skin depth is, resulting in an increase in the resistance of the conductor. The skin depth is inversely proportional to the square root of frequency.

The equivalent parallel conductance G is also called Dielectric Loss. At low frequencies, the equivalent parallel conductance is related to the bulk conductivity and the equivalent capacitance of the dielectric. When the frequency increases, the dielectric loss angle begins to play a leading role. At this time, the dielectric conductivity is determined by dielectric loss angle and signal frequency.

In general, when the frequency is less than 1GHz, the skin effect loss plays a major role, and when the frequency is above 1GHz, the dielectric loss dominates.

The dielectric constant, dielectric loss angle, conductor conductivity and cut-off frequency can be set in the simulation software. The software will consider the skin effect and dielectric loss according to the structure of the transmission line during simulation. If the attenuation is simulated, the corresponding cut-off frequency must be set according to the bandwidth of the signal. The bandwidth is determined by the edge rate of the signal. There is little difference between the edge rate of many 622MHz signals and 2.5GHz signals. In addition, it can be seen in the model of lossy transmission lines that the equivalent resistance and conductance vary with the frequency rate.

It can be seen from Figure 2 that the loss slows down the rising edge of the signal, that is, reduces the bandwidth of the signal, and the loss reduces the amplitude of the signal. On the other hand, it is beneficial to suppress signal overshoot.

Crosstalk of transmission lines also affects the loss. Crosstalk depends on the physical structure of transmission lines, coupling length, signal strength and edge rate. After a certain length, the crosstalk will be saturated, but the loss will not necessarily increase.

Effects of vias and connectors

The via transmits the signal to the other side of the board. The vertical metal part between the boards is an uncontrollable impedance, and the inflection point that changes from the horizontal direction to the vertical direction is a breakpoint, which will generate reflection. It should be minimized (Figure 3).

In the design and simulation of gigabit system, the via model is needed to consider the influence of via. The model structure of vias is in the form of series resistance R, inductance L and parallel capacitance C. According to the specific application and accuracy requirements, multiple RLC structures can be used in parallel, and the coupling with other conductors is considered. At this time, the via model is a matrix.

There are two ways to obtain the via model: one is through testing, such as TDR, and the other is through 3D Field Solver according to the physical structure of the via.

Through hole model parameters are related to PCB material, lamination, thickness, pad/reverse pad size, and the connection mode of the connecting line. In the simulation software, different parameters can be set according to the accuracy requirements, and the software will extract the via model according to the corresponding algorithm and consider its impact during simulation.

In the design of gigabit system PCB, the influence of connectors should be particularly considered. Now the development of high-speed connector technology can well ensure the continuity of impedance and ground plane during signal transmission. The simulation analysis of connectors in the design mainly adopts the multi line model.

The connector multi wire model is extracted in three-dimensional space by considering the inductance and capacitance coupling between pins. The RLGC matrix of connector multi line model is generally extracted by 3D field extractor, which is generally the form of Spice model sub circuit. Due to the complex structure of the model, it takes a long time to extract and simulate. In SpectraQuest software, you can edit the Spice model of the connector into an Epice model and assign it to the device or call it directly, or edit it into a DML format packaging model and assign it to the device for use.

Differential signal and wiring consideration

Differential signal has the advantages of strong anti-interference and high transmission rate. In gigabit signal transmission, it can better reduce the impact of crosstalk, EMI, etc. Its coupling forms include edge coupling, upper and lower coupling, loose coupling and tight coupling.

Compared with up and down coupling, edge coupling has the advantages of better crosstalk reduction, convenient wiring and simple processing. Up and down coupling is more often applied to PCB boards with high wiring density. Compared with loose coupling, tight coupling has better anti-interference ability and can reduce crosstalk, while loose coupling can better control the continuity of differential line impedance.

The specific differential routing rules should consider the influence of impedance continuity, loss, crosstalk, and routing length difference according to different situations. It is better to use eye diagram to analyze the simulation results. The simulation software can set random sequence code to generate eye diagram, and can input jitter and offset parameters to analyze their impact on eye diagram.

Power distribution and EMC

The improvement of data transmission rate is accompanied by faster edge rate, which needs to ensure power supply stability in a wider band. A high-speed system may pass transient 10A current, and the maximum ripple of the power supply is required to be 50 mV, which means that the impedance of the power distribution network within a certain frequency range should be guaranteed to be within 5 m Ω. For example, the rise time of the signal is less than 0.5 ns, and the bandwidth range to be considered is 1.0 GHz.

In the design of gigabit system, synchronous noise (SSN) interference should be avoided to ensure that the power distribution system has a low impedance within the bandwidth. Generally, decoupling capacitor is used to reduce impedance in low frequency band, and power supply and ground plane distribution are mainly considered in high frequency band. Figure 4 shows the frequency response diagram of impedance change when decoupling capacitance is considered or not considered for power supply and ground layer.

SpecctraQuest software can analyze the impact of synchronous noise caused by packaging structure. Power Integrity (PI) software uses frequency domain analysis power distribution system, which can effectively analyze the number and location of decoupling capacitors and the impact of power supply and ground plane, helping engineers to select decoupling capacitors and analyze their placement, wiring and plane distribution.

EMC refers to electromagnetic compatibility. The problems generated include excessive electromagnetic radiation and susceptibility to electromagnetic radiation. The main reasons are that the working frequency of the circuit is too high and the layout is unreasonable. At present, there are software tools for EMC simulation, but EMC problems can be caused by many electromagnetic reasons. It is difficult to set simulation parameters and boundary conditions, which will directly affect the accuracy and practicality of simulation results. The most common approach is to apply the design rules that control EMC to each link of the design, to achieve rule driving and control in each link of PCB design. After the design is tested and verified, new rules can be formed and applied to the new design.

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