How to Select Capacitor Combinations in PCB Design
As we mentioned earlier, the change of transient current is equivalent to a step signal and has a wide spectrum. Therefore, in order to compensate for this current demand, it is necessary to provide suffICient low power impedance in a wide frequency range. However, the effective frequency range of different capacitors is different, which is related to the resonant frequency of the capacitor (strictly speaking, it should be the resonant frequency after installation). The effective frequency range (the frequency range that the capacitor can provide enough low impedance) is a SMAll frequency near the resonant point. Therefore, to provide low enough power impedance in a wide frequency range, many different capacitor combinations are required.
You may say that with only one capacitance, as long as the number of parallel capacitors is enough, the impedance can be the same low. It is true, but in practical applications you can calculate that most of the time, the required capacitance is very large. If you really want to do this, your circuit board may be full of capacitors. It is neither professional nor necessary.
There are many problems to consider when selecting capacitor combination, such as what package to choose, what material, how large the capacitance value, how large the interval between capacitance values, what is the main clock frequency and its harmonic frequencies, and the signal rise time, which need to be specially designed according to the specifIC design.
In general, tantalum capacitors or electrolytic capacitors are used for board level low frequency decoupling. The calculation method of capacitance has been mentioned before. It should be noted that it is better to use several or more capacitors in parallel to reduce the equivalent series inductance. The Q value of these two capacitors is very low, and the frequency selectivity is not strong, so they are very suitable for board level filtering.
The selection of high frequency small capacitors is somewhat troublesome and requires frequency division calculation. The frequency range to be decoupLED can be divided into several sections. Each section is calculated separately. Multiple capacitors with the same capacitance value are used in parallel to meet the impedance requirements. Different capacitance values are selected for different frequency bands. However, in this method, the division of frequency band should be constantly adjusted according to the calculation results.
Generally, it can be divided into three to four frequency bands, which requires three to four capacity levels. In fact, the more capacitance levels selected, the flatter the impedance characteristics. However, it is unnecessary to use a lot of capacitance levels. Of course, the flatness of impedance is good, but our ultimate goal is that the total impedance is less than the target impedance, as long as this requirement can be met.
The capacity value selected in a certain level depends on the system clock frequency. As mentioned earlier, there is anti resonance in the parallel connection of capacitors. During the design, pay attention not to let the harmonics of the clock frequency fall near the anti resonance frequency. For example, if 0.47, 0.22, 0.1 or other values are selected for the zero point method level, the resonant frequency after the following installation shall be calculated.
Another point to note is that the rating of the capacity value should not exceed 10 times. For example, you can choose a combination like 0.1, 0.01 and 0.001. Because this can effectively control the amplitude of the anti resonance point impedance. If the interval is too large, the anti resonance point impedance will be large. Of course, this is not absolute. It is better to use software to see that the ultimate goal is that the impedance of the anti resonance point can meet the requirements.
The selection of high frequency small capacitors is a process of iterative search for the optimal solution in order to obtain the optimal combination. The best way is to roughly calculate the approximate combination, then use the power integrity SIMulation software for simulation, and then make local adjustments to meet the target impedance requirements. This is intuitive and convenient, and it is easier to control the anti resonance point. Moreover, the capacitance of the power plane can also be added for joint design.
Ceramic capacitors are generally selected in the conventional design of medium with small capacitance. The ESR of NP0 dielectric capacitor is much lower. It can be used locally with more strict impedance control. However, it should be noted that the Q value of this capacitor is very high, which may cause serious high-frequency ringing.
As long as the processing capacity allows, the smaller the package, the better. In this way, lower ESL can be obtained and more wiring space can be reserved. However, different packages have different resonant frequency points and capacitance ranges, which may affect the final capacitance. Therefore, the capacitor package size and capacitance value should be considered jointly. In short, the ultimate goal is to achieve the target impedance requirements with the least capacitance, reducing the pressure of installation and wiring. PCB assembly and PCB processing manufacturers explain how to reasonably select capacitor combination in PCB design.