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Mobile phone PCB wiring layout has risks and should be cautious
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Mobile phone PCB wiring layout has risks and should be cautious

Mobile phone PCB wiring layout has risks and should be cautious

The Circuit board manufacturer and circuit board designer explain the PCB wiring of mobile phones

1、 What problems should we pay attention to in mobile phone PCB layout? Is there any display part that needs wiring?

Layer1: devICe

Layer2: signal Most of the addresses, data signals, and some analog lines (the corresponding three layers are ground)

Layer3: GND part wiring (including the keyboard surface and the wiring that cannot be removed from Layer 2), GND

Layer4: The stripline needs to pass through RF baseband analog control lines (txramp_rf, afc_rf), audio lines, analog interface lines between baseband master chips, and master clock lines

Layer5: GND GND

Layer6: power layer VBAT, LDO_ 2V8_ RF(150mA)、VMEM(150mA)、VEXT(150mA)、VCORE(80mA) 、VABB(50mA)、VSIM(20mA) 、VVCXO(10mA)

Layer7: routing of signal keyboard

Layer8: Devices


2、 Specific wiring requirements

1. General principles:

Wiring sequence: RF ribbon line and control line (at the antenna) -- baseband RF analog interface line (txramp_rf, afc_rf) -- baseband analog line including audio line and clock line -- analog baseband and digital baseband interface line -- power line -- digital line.

2. Wiring requirements for RF ribbon line and control line

The RFOG and RFOD networks are the striplines of the fourth layer, with a line width of 3mil. The upper and lower layers are covered by land. The width of the stripline is determined according to the actual plate thickness and routing length; As the stripline needs to be punched with 2~7 holes, pay attention that the bottom layer is wrapped with land near these holes, and the routing of other layers should not be too close to these holes;

RX_ GSM、RX_ DCS、RX_ The PCS network is the RF receiving signal line on the top floor, with the line width of 8mil; RFIGN, RFIGP, RFIDN, RFIDP, RFIPN, and RFIPP networks are the RF receiving signal lines on the top layer and the second layer. The fixed layer line width is 8mil, and the second layer line width is 4mil;

GSM_ OUT、DCS_ OUT、TX_ GSM、TX_ The DCS/PCS network is the top power amplifier output transmission signal line, and the line width should be 12 mils;

The top signal line ANT from the antenna switch output to the test base and antenna contact_ 1、ANT_ 2、ANT_ 3. ANT, the line width should be 12 mils.

3. Analog line with RF interface (four layers)

TXRAMP_ RF、AFC_ The routing of RF network shall be thickened as much as possible, and the two sides shall be surrounded by ground wires, and the line width shall be 6mil;

QN_ RF、QP_ RF; IN_ RF、IP_ RF refers to two pairs of differential signal lines. The line length should be as equal as possible and the spacing should be as equal as possible. The wiring width on the fourth floor is 6mil.

4. Important clock line (four layers)

The 13MHz crystal U108 and the quartz crystal G300 are noise sensitive circuits. Please minimize the signal wiring below.

Two terminals OSC32K of quartz crystal G300_ IN、OSC32K_ Pay attention to parallel routing during OUT line stepping, and the closer to D300, the better. Please note that the input and output lines of the 32K clock must not cross.

SIN13M_ RF、CLK13M_ IN、CLK13M_ T1、CLK13M_ T2、CLK13M_ IN_ X、CLK13M_ The routing of the OUT network should be as short as possible, and the two sides should be surrounded by ground wires. The adjacent two layers of the routing should be grounded.

The clock is recommended to go 8mil

5. The following baseband analog lines (four layers)

The following are 8 pairs of differential signal lines:



To avoid phase error, the line length shall be as equal as possible, and the spacing shall be as equal as possible.

BATID is AD sampling analog line, please walk 6mil;

The four analog lines TSCXP, TSCXM, TSCYP, and TSCYM are also routed according to the differential signal line. Please go 6mil.

6. AGND and GND distribution (?)

AGND and GND networks are not connected together in the schematic diagram. After the cloth board is completed, it is connected with copper foil. The specific location is as follows:

The bottom of D301 chip is distributed as analog AGND. The analog AGND and digital GND are connected near the AGND (PIN G5) of D301.

The bottom of D400 chip is distributed as MIDI analog MIDIGND, and MIDI analog MIDIGND and digital GND are connected near the 16 pin of D400.

AGND should preferably be above 50mil.

8. Important interface lines between digital baseband and peripheral devices

LCD_ RESET、 SIM_ RST、CAMERA_ RESET、MIDI_ RST、NFLIP_ DET、MIDI_ IRQ、IRQ_ CAMERA_ IO、IRQ_ CAMERA_ IO_ 10. PENIRQ is a reset signal and an interrupt signal. Please use a wire of at least 6mil.

POWE_ ON/OFF runs at least 6mil.

7. Important interface lines between digital baseband and analog baseband:

VSDI, VSDO, VSFS, BSIFS, BSDI, BSDO, BSOFS, ASDI, ASFS, ASDO are high-speed data lines. The lines should be as short and wide as possible (more than 6mil), and copper should be coated around the lines;

BUZZER、ASM、ABB_ INT、RESET、ABB_ RESET is an important signal wire. Please go through at least 6mil of wire, short and copper coated around the wire;

9. Power supply:

(1) Power signal with large load current (six layers): the load current of the following power signals decreases in turn, and it is better to divide them at the power layer: CHARGE_ IN、VBAT、LDO_ 2V8_ RF (150mA), VMEM (150mA), VEXT (150mA), VCORE (80mA), VABB (50mA), VSIM (20mA), VVCXO (10mA), VBAT, CHARGE when wiring is required_ IN is better than 40.

(2) Power signal with SMAll load current: VRTC and VMIC have small current, which can be distributed on the signal layer.

(3) Charging circuit: VBAT, CHARGE connected to XJ600_ IN, ISENSE power transmission line connected to VT301, with large current, please lay the line wider, and it is recommended to be 16mil.

(4) Keyboard backlight: KB_ BACKLIGHT、KEYBL_ T1 has a current of 50mA. The current flowing through R802~R809 and VD801~VD808 is 5mA. Pay attention when routing.

(5) Motor drive: VIBRATOR, VIBRATOR_ X The network current is 100mA.

(6) LCD backlight drive: LCD_ BL_ CTRL、LCD_ BL_ CTRL_ The current flowing through the X network is 60mA

(7) Seven color lamp backlight drive: LPG_ GREEN、LPG_ RED、LPG_ BLUE、LPG_ RED_ FPC、LPG_ GREEN_ FPC、LPG_ BLUE_ FPC、LPG_ RED_ FPC_ x、LPG_ GREEN_ FPC_ x、LPG_ BLUE_ FPC_ X The current flowing through the network is 5mA, and it is recommended to go 6mil; LPG_ The current flowing through the OUT is 20mA. It is recommended to run more than 8 mils, and stay away from analog signal wiring and via.

10. About EMI routing

(1) Before arriving at XJ700, the output networks of Z701, Z702 and Z703 should walk on the inner layer, try to walk on the second layer, and then punch via2~1 near the XJ700 pin to the TOP layer.

(2) Network LPG from RC filtering_ RED_ FPC_ x、LPG_ GREEN_ FPC_ x、LPG_ BLUE_ FPC_ x、VIBRATOR_ x、NCS_ MAIN_ LCD_ x、NCS_ SUB_ LCD_ x、ADD01_ X Before arriving at XJ700, please walk on the inner layer, walk on the third or sixth or seventh layer, and then punch holes near the XJ500 pins to the TOP layer.

(3) The network of the keyboard matrix cannot be routed on the eighth floor. Try to walk on the seventh floor. If you can't walk down the seventh floor, you can go to the third floor.

(4) The wiring of the earphone at the bottom and top of the keyboard surface shall be minimized on the eighth floor. I hope the keyboard surface can be paved in a large area.

(5) The SIM card XJ601 should be paved as much as possible below (on the surface), with less signal lines.

11. The shielding strip around the components is 0.7mm, the spacing between shielding strips is 0.3mm, and the bonding pad is 0.4mm away from the shielding strip. This position has been reserved.

12. There are two BGA devices in the baseband. Since the BGA conductive adhesive can only be dropped from one direction, the RF surface is taken as the front, and a 0.7mm glue drop position is reserved on the left side of the BGA.

13.20H principle. The power plane is indented 20H from the ground plane.

14. Size of vias: 0.3mm/0.1mm for layers 1~2, 7~8, and 0.55mm/0.25mm for other vias.

15. The edge of the top layer PCB shall be provided with a 1.5-2mm wide grounding strip and punched.

16. After copper coating, connect the ground of each layer with via.

17. Pay attention to avoid parallel routing of adjacent layers as much as possible, especially for the fourth layer, the third layer should be particularly careful.