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Development of substrates for printed circuit boards
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Development of substrates for printed circuit boards

The basic characteristics of printed circuit board depend on the performance of the substrate board, to improve the technical performance of printed circuit board must first improve the performance of printed circuit substrate board, in order to meet the needs of the development of printed board, a variety of new materials are gradually developed and put into use.

In recent years, PCB market focus has shifted from computer to communication, including base station, server and mobile terminal, etc. Mobile communication equipment represented by smart phone drives PCB to higher density, thinner and higher function development. Printed circuit technology can not be separated from the substrate material, which also involves the technical requirements of PCB substrate. The substrate material related content is now sorted into a special article for CCL industry reference.

1. Demand for high density fineness

1.1 Demand for copper foil

PCB all to high density fine line development, HDI board is particularly prominent. Ten years ago IPC for HDI board under the definition of line width/line distance (L/S) is 0.1mm/0.1mm and below, now the industry basically do conventional L/S for 60μm, advanced L/S for 40μm. The Japanese installation technology roadmap for the 2013 edition shows that the conventional L/S of the 2014 HDI board is 50μm, the advanced L/S is 35μm, and the pilot L/S is 20μm.


PCB circuit pattern formation, the traditional copper foil substrate after photoimaging chemical etching process (reduction method), the reduction method of fine line production limit is about 30μm, and need to use thin copper foil (9~12μm) substrate. Due to the high price of thin copper foil CCL and the high lamination defects of thin copper foil, many factories produce 18μm copper foil and then use etching to reduce the copper layer in production. This method has many processes, difficult thickness control and high cost. It is better to use thin copper foil. In addition, PCB line L/S is less than 20μm, the general thin copper foil is also difficult to do, need to use ultra-thin copper foil (3~5μm) substrate and attached to the carrier ultra-thin copper foil.

The current fine line requirements of copper foil in addition to thinner thickness, at the same time need copper foil surface roughness. In order to improve the binding force between copper foil and substrate and ensure the stripping strength of conductor, coarsening of copper foil layer is usually adopted. The conventional copper foil roughness is greater than 5μm. Copper foil rough convex peak embedded in the substrate is to improve the stripping resistance, but in line etching to control wire precision is not too etching, it is easy to embed the substrate convex peak residue, resulting in short circuit between the lines or insulation decline, especially for fine lines. Copper foils with low roughness (less than 3μm) and even lower roughness (1.5μm) are required. However, the roughness of copper foil decreases while the anti-stripping strength of the conductor still needs to be maintained. Special treatment is needed for the surface of copper foil and substrate resin. If there is a smooth resin surface electroless plating copper foil with high binding force; If there is "molecular bonding technology", is the chemical treatment of the surface of the resin substrate to form a functional group can be closely combined with the copper layer.

1.2 Requirements for laminated insulating dielectric sheets

HDI board technology is characterized by BuildingUpProcess, commonly used resin coated copper foil (RCC), or semi-cured epoxy glass cloth and copper foil lamination is difficult to reach fine lines. Now tends to use semi-addition method (SAP) or improved semi-processing method (MSAP), that is, the use of insulating medium film layer, and then electroless copper plating to form copper conductor layer, because the copper layer is extremely thin and easy to form fine lines.

One of the key points of the semi-addition method is the laminated dielectric material. In order to meet the requirements of high density and fine lines, the laminated material is proposed to meet the requirements of dielectric electricity, insulation, heat resistance, binding force and so on, as well as the process adaptability with HDI board. At present, ABF/GX series products of Ajinomoto Company are the main HDI stacking medium materials in the world. Epoxy resin is combined with different curing agents, inorganic powder is added to improve material rigidity and reduce CTE, and glass fiber cloth is also used to enhance rigidity. A similar thin film lamination material was developed by the Japanese Water Chemical Company and by the Taiwan Institute of Industrial Research. ABF materials also continue to improve and develop, the new generation of laminated materials in particular requires low surface roughness, low thermal expansion rate, low dielectric loss and thin hardening.

In semiconductor packages around the world, IC packaging boards have been replaced by organic substrates instead of ceramic ones. Flip chip (FC) packaging boards have increasingly smaller pitch, with typical line width/line spacing now 15μm, and will be thinner in the future. The performance of multilayer carrier plate requires low dielectric property, low thermal expansion coefficient and high heat resistance, and low cost substrate is pursued on the basis of meeting the performance objectives. At present, the mass production of fine line basically adopts the MSPA process of insulating medium layer combined with pressed thin copper foil. SAP method is used to fabricate circuit patterns with L/S less than 10μm.

When PCB is thicker and thinner, HDI board technology develops from core-containing layer to non-core-containing Anylayer. The area and thickness of HDI board with the same function can be reduced by about 25% compared with that of HDI board with core-containing layer. These must use thinner dielectric layers that retain good electrical properties.

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