IC design: CMOS devices and **their circuits**

(PMOS should have a small circle at the symbol grid * to indicate that the level is low.)

③ The circuit symbol and working principle of (two-input) CMOS or NOR are as follows:

IC design: CMOS devices and their circuits

(PMOS should have a small circle at the symbol grid * to indicate that the level is low.)

All **digital logic circuits** can be simplified by the above three kinds of circuits, that is to say, a circuit can be composed of NAND or NOR circuits. Let's take a look at their characteristics to deduce the characteristics of digital CMOS circuits.

Easy to know (let's take that as a conclusion anyway) :

The general structure of a reverse logic gate is as follows:

IC design: CMOS devices and their circuits

In addition, we also note that NMOS networks are in series when used with functions; In use or function, the NMOS network is in parallel. So you can remember that you need all of the NOMS to be together, you need only one of the NMOS to be together (or), and or or, depending on the string union structure of the NMOS.

Then design how many input NXXX gate, the number of NMOS string/parallel, and then PMOS is and/string can be.

4. CMOS power consumption representation

Power consumption refers to the energy consumed per unit time. Power consumption in digital systems mainly includes static power consumption and dynamic power consumption. We will discuss static power consumption and dynamic power consumption from the perspective of **CMOS circuits**.

CMOS static power consumption: Power consumption when the CMOS is not flipping/not working. When the CMOS is not working, that is, when the transistors are in the cut-off state, there is no current flowing from VDD to GND, but there is still some small current flowing from the source to the ground. This static current Idd is called the leakage current between the power source and the ground, which is related to the device (as to how the leakage current is caused, it will not be explained here). In junior high school, we learned that P=UI, so static power consumption can be expressed like this:

IC design: CMOS devices and their circuits

The dynamic power consumption of CMOS is the power consumed by capacitor charging and discharging when the signal changes between 0 and 1. As we know, not only CMOS devices have parasitic capacitors, but also capacitance between wires. CVdd^2 is the energy required to charge capacitor C to voltage Vdd. If the capacitor transforms f times per second (that is, the capacitor switches at a frequency of f, and in one second the capacitor charges f/2 times and discharges f/2 times), since the discharge does not require power from the supply, the dynamic power can be expressed as follows:

IC design: CMOS devices and their circuits

PS: The above list mainly lists some major power consumption. For example, in dynamic power consumption, in addition to the capacitor power consumption when flipping, there is also the short-circuit power consumption caused by the simultaneous on-off of PMOS and NMOS when the gate * signal is flipping.

**Chip heating**

This is mainly for high voltage driver chips with built-in power modulators. If the current consumed by the chip is 2mA, 300V voltage is applied to the chip, and the power consumption of the chip is 0.6W, of course, it will cause the heat of the chip. The large current of the driver chip comes from the consumption of the driving power MOS tube. The simple calculation formula is I=cvf.

Considering the resistance benefit of charging, the actual I=2cvf, where c is the cgs capacitance of the power MOS tube and v is the gate voltage when the power tube is switched on. Therefore, in order to reduce the power consumption of the chip, try to reduce c, v and f. If c, v, f cannot be changed, then please find a way to distribute the power of the chip to the off-chip device. Be careful not to introduce additional power consumption. Another simple point is to consider the best heat dissipation.

The power consumption of power tube is divided into two parts, switching loss and on-off loss. Note that most occasions, especially LED mains drive applications, switch damage is far greater than the on-off loss. The switching loss is related to the cgd and cgs of the power tube as well as the driving capacity and working frequency of the chip, so the heating of the power tube can be solved from the following aspects:

01. MOS power tube can not be selected unilaterally according to the size of the on-off resistance, because the smaller the internal resistance, the larger the capacitance of cgs and cgd.

For example, cgs for 1N60 is about 250pF, 2N60 cgs is about 350pF, 5N60 cgs is about 1200pF, the difference is too big, when choosing a power tube, enough is enough.

02, the rest is frequency and chip drive capability, here only talk about the effect of frequency. Frequency is also proportional to conduction loss, so when the power tube heating, * to think about whether the frequency selection is a little high. Find a way to lower the frequency!

However, it should be noted that when the frequency decreases, in order to obtain the same load capacity, the peak current must be increased or the inductance must also be increased, which may lead to the inductance entering the saturation region. If the inductance saturation current is large enough, you can consider changing CCM (continuous current mode) to DCM (discontinuous current mode), so you need to add a load capacitor.