Because the insulation between the layers is so thin, the impedance between layers of 10 or 12 boards is very low, and excellent signal integrity is expected as long as the layering and stacking are not problematic. It is difficult to process and manufacture 12-layer plates with a thickness of 62mil, and there are not many manufacturers capable of processing 12-layer plates.
Since there is always an insulating layer between the signal layer and the loop layer, it is not optimal to allocate the middle six layers to route the signal line in the 10-layer board design. In addition, it is important to have the signal layer adjacent to the loop layer, that is, the board layout is signal, ground, signal, signal, power, ground, signal, signal, signal, signal.
This design provides a good path for signal current and its loop current. The proper routing strategy is to route the first floor in the X direction, the third floor in the Y direction, the fourth floor in the X direction, and so on. Visually, Layers 1 and 3 are a pair of layers, Layers 4 and 7 are a pair of layers, and Layers 8 and 10 are the last pair of layers. When the direction of the line needs to be changed, the signal line on Level 1 should be changed by "through the hole" to Level 3. In practice, you may not always be able to do this, but as a design concept, try to follow it.
Similarly, when the line direction of the signal changes, it should go from layers 8 and 10 or from layers 4 to 7 by passing through holes. This wiring ensures the tightest coupling between the forward path and the loop of the signal. For example, if the signal is routed on the first layer and the loop is routed on the second layer and only on the second layer, then even if the signal on the first layer is transferred to the third layer by "through the hole", its loop is still in the second layer, thus maintaining the characteristics of low inductance, large capacitance and good electromagnetic shielding performance.
What if the actual route is not like this? For example, the signal line on the first layer through the hole to the 10th layer, then the loop signal had to find the grounding plane from the 9th layer, the loop current to find the nearest grounding hole (such as resistance or capacitor and other components of the grounding pin). If you happen to have one nearby, you're really lucky. If there is no such a close through hole available, the inductance will be larger, capacitance to reduce, EMI must increase.
When the signal line must leave the present pair of wiring layers to other wiring layers through the hole, the ground hole should be placed near the hole, so that the loop signal can be smoothly returned to the appropriate grounding layer. For layers 4 and 7, the signal loop will return from the power layer or ground layer (i.e., layer 5 or 6) because the capacitive coupling between the power layer and ground layer is good and the signal is easily transmitted.
If two power layers of the same voltage source need to output high current, the circuit board should be distributed into two groups of power layers and grounding layers. In this case, an insulating layer is placed between each pair of power layer and ground layer. This gives us the desired two pairs of power busbars with equal impedances for equal currents. If the stack of power layers results in unequal impedance, the shunt will be uneven, the transient voltage will be much larger, and EMI will increase dramatically.
If there are multiple power supply voltages with different values on the circuit board, multiple power layers are required accordingly. Remember to create separate power layers and connections for each power supply. In both cases, keep in mind the manufacturer's requirements for balanced structure when determining the position of the paired power layer and ground layer on the board.
Given that most of the circuit boards designed by engineers are traditional printed circuit boards with a thickness of 62mil and no blind or buried holes, the discussion of layering and stacking of circuit boards is limited here. The layered scheme recommended in this paper may not be ideal for boards with large thickness differences. In addition, the fabrication process of circuit boards with blind holes or buried holes is different, so the layering method in this paper is not applicable.
In circuit board design, the thickness, through hole process and the number of layers of circuit board are not the key to solve the problem. Good layered stacking is the key to ensure the bypass and decoupling of the power busbar, to minimize the transient voltage on the power layer or ground, and to shield the electromagnetic field of the signal and power. Ideally, there should be an insulating layer between the signal routing layer and the loop grounding layer, and the spacing of the paired layers (or more than one pair) should be as small as possible. According to these basic concepts and principles, can always be designed to meet the design requirements of the circuit board. Now that the rise time of IC is already short and will be shorter, the techniques discussed in this article are essential to solving EMI shielding problems.