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Look at the signal integrity design tool of high-speed PCB system
02Jan
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Look at the signal integrity design tool of high-speed PCB system

When high-speed data is transmitted through long PCB wires, it is easy to be distorted due to the influence of dielectrIC loss. It is difficult to solve many SI/EMI design problems in the GHz band with traditional rules. This paper introduces the method of hierarchical design rules and loss prediction of circuit boards by means of SpectraQuest tool, and verifies the device model with HSPIce tool, analyzes the power and ground plane of the selection and layout of decoupling capacitors, and obtains the precise geometric parameters of special wiring/component structures with Maxwell 2D and 3D field solving tools.

With the increasing complexity of high-speed PCB design in communication systems, it is impossible to complete the entire design SIMulation in an acceptable accuracy range relying on a specific CAD tool. PCB design engineers and signal integrity (SI) design engineers need to use various simulation tools. In addition to price, performance, speed and accuracy are always the main criteria for selecting tool sets, how to use CAD tools from multiple EDA tool software suppliers to achieve design goals, SI and electromagnetic interference (EMI) design rules is also an important issue of concern to Chinese design engineers. In general, the combination of good design and SI/EMI analysis tools should include: layout design tools, board level simulators, accurate field solving tools and detaiLED simulation engines.

The tools discussed in this paper include: Allegro and SpectraQuest, Hspice, Spicelink and HFSS: Allegro is a general layout design tool at present; With the same database as Allegro, SpecctraQuest is used as the main tool of board level simulation to avoid the problem of data conversion; Hspice is a tool for more accurate analysis; Spicelink and HFSS provide 2D and 3D field solutions to analyze various interconnection geometries (vias, connectors, etc.), especially when high-frequency analysis is required.

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In order to effectively use the existing CAD tools, the corresponding tools should be selected at the appropriate design stage. Taking the high-speed communication system with the transfer rate of 2.5Gbps to 12.5Gbps between the card and the motherboard as an example, this paper introduces how to correctly use a variety of simulation tools to solve the PCB design problem with the speed of Gbps.

1、 Creating Design Rules with SpectraQuest

Allegro is a layout design tool, and SpecctraQuest is a board level simulation tool. The advantages of the combination of the two tools lie in sharing the same huge database, using the same simulation engine and similar graphical user interface. As Allegro and SpecctraQuest are further integrated, design engineers can conduct layout design and simulation at the same time in the design phase. In order to enable the designed card and backplane to transmit 2.5Gbps serial data signals with edge rate of 100ps-200ps, it is necessary to master the SI problems in this frequency band and manage them effectively. The main SI problems to be understood include skin effect, dielectric loss, coupling and driver pre emphasis. The SpecctraQuest tool can simulate and solve the following problems:

a. The SignalExplorer tool is used for pre layout analysis and extraction of important nodes. With the increasing complexity of circuit boards, pre layout analysis and design rule setting become more and more important. By using SpecctraQuest circuit diagram extraction tool, SignalExplorer can perform pre layout analysis according to circuit parameter changes, and extract important network nodes into the circuit browser, so as to check the wiring and layout later design. Like many other circuit level simulation tools, one of the disadvantages of SpecctraQuest is the lack of detailed modeling capability. In other words, IBIS model is the only device model that can be used. Therefore, the behavior model must be reliably evaluated before analysis in SignalExplorer.

The following problems can be solved by using SignalExplorer: evaluating the geometric size of the circuit board layering, estimating the skin effect and the loss caused by the medium, giving the design rules for the allowable line length of high-speed data/clock, giving the line spacing for controlling coupling, giving the terminal type and value, and the maximum miSMAtch length of all differential pairs. Experience shows that the design rules obtained from the above simulation can provide valuable guidance for engineering layout and routing, thus greatly shortening the design cycle and reducing the design risk.

b. Losses and compensation

Skin effect and dielectric loss are generally considered as the main problems in the design of gigabit data transmission board. The skin effect determines the width of the line, and the dielectric loss depends on the material constituting the PCB. To solve these two basic problems, the board level simulator must have the ability to handle lossy transmission lines with independent frequency parameters. SpecctraQuest meets this requirement. The simulation and measurement results show that the dielectric loss is dominant in the GHz band.

In communication systems, high-speed data is transmitted through long wires, so it is easy to be distorted by the influence of dielectric loss. One way to overcome this loss effect is to use an equalizer and a pre weighting device. There are several kinds of equalization methods to choose from. This paper only discusses the equalization circuit using passive components. Because most devices have built-in equalization circuits, IBIS model is difficult to compensate them.

By separating the passive components from the components and putting them on the circuit board, we can simulate the equalization effect. Using SpecctraQuest to analyze the modified netlist, you can obtain a general guide for equalizer application.

When the influence of the medium is small, the equalizer should not work. The function of equalizer is to compensate the loss of high-frequency components on long interconnects. Preemphasis may lead to deterioration of the eye diagram of shorter interconnects. With the growth of interconnects, the dielectric loss of FR4 plates will become larger and larger. The high-frequency component of the signal (corresponding to the steep rising/falling edge) will disappear, while the low-frequency component will be retained. In order to effectively use the pre emphasis function, it is necessary to first estimate the length of the interconnects on the signal transmission path, and then decide whether to take compensation measures. It is not optimal to pre emphasize all interconnects with high transmission rate.

When 2.5Gbps signals pass through different lengths of differential interconnects, the differences of eye diagram window and jitter are compared when the pre adder is on/off.

c. Coupling in GHz band

When the data rate is lower than Gbps, coupling is always the main factor affecting the noise index in PCB design. Since the frequency component of the coupling signal is higher than that of the intrusion signal, its loss is greater than that of the original Gbps signal, and its impact on the noise index is naturally reduced.

Most layout design tools estimate the effect of coupling based on the coupling coefficient determined by the routing geometry and PCB material, which leads to a linear estimation formula limiting the parallel distance, which reduces the routing density. In fact, the coupling will reach saturation state on long wiring. Ignoring the saturation effect in the estimation process will lead to more intensive routing design rules than required. Therefore, SpecctraQuest should be used for comprehensive simulation to determine the coupling rules in the design.

For 2.5Gbps data, the typical rise time is 150ps, and the saturation length is about 300mil, which means that the actual coupling line can be longer than 300mil without increasing the coupling budget value. Table 2 shows the coupling saturation parameters and losses of signals with 2.5Gbps rate, 500mv swing and 110ps rise time. The coupling reaches saturation at about 300-400mil, because the loss makes its amplitude attenuate greatly on the long wiring. According to this rule, design engineers can route more effectively, which is more effective than the design rules given by many layout design tools.

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2、 Using Maxwell 2D/3D to Design Complex Cabling Structure

For higher transmission rates ranging from 10G to 12.5Gpbs, FR-4 plates will produce large losses. Other plates with better loss characteristics should be used. As shown in Figure 1, a circuit board with coplanar structure is used to transmit data from 10Gbps to 12.5Gbps on the top of the circuit board. The board used is RO4350. The dielectric loss of this board is very low, but it can only be wired on the top/bottom PCB, so the surface layer wire is used for transmitting 10GHz signals. The coplanar structure has good signal quality and low EMI. The 3D field solver shall be used to calculate the line width and spacing to ensure a 50 ohm line impedance that matches the output impedance of the drive circuit. Maxwell 3D field solver can be used.

3、 Connector modeling

When signals are transmitted at Gbps data rate, vias, connectors, and related wires will cause signal integrity problems. Accurate modeling and simulation of connectors and vias are very important for predicting signal quality.

Maxwell 3D field solver is used to extract VHDM and HSD models of the connector. After the connector model is established, it should be embedded in SpectraQuest DML format for board level simulation of Hspice sub circuits. Generally speaking, even if a Gbps card is successfully designed, there are still many challenges to design a backplane with a transmission rate of 5-10Gbps. Maxwell Field Solver helps to create connector models for such data rates.

4、 Detailed analysis with Hspice

A. Use Hspice for power layer analysis

In the GHz band, power transmission is facing new challenges, and precise modeling techniques and analysis tools should be used to obtain real (power) plane response. Hspice is a tool that can realize precise frequency sweep analysis, and has a transistor based IC model to simulate the interesting concurrent switching noise (SSN).

For the power layer transmitting power to the high-frequency differential element, the transmission line mesh model can be used to evaluate the behavior of the power/ground plane at high frequencies. For example, to analyze a pair of 2 inches in a PCB × 2.5 inch power/ground plane, with plane spacing of 3.5mil, edge rate of 70ps and bandwidth of 5GHz. In general, the target impedance budget of each differential power/ground plane pair is 272m? According to the parameter index of a main differential element?, Is the transmission line mesh model used to determine the power supply? Frequency domain response of the ground plane. For speeds above 1Gbps, it is recommended to consider lossy and lossless conditions respectively to determine the impact of adding media loss to the model.

The model is used for Hspice simulation, and the resonant frequency obtained is 1.2GHz. The simulation results show that by considering the dielectric loss on the power/ground plane, the resonant amplitude can be greatly reduced, which is helpful for the frequency domain response of the power/ground plane to meet the requirements of the target impedance. Since most high-speed serial data are transmitted in differential mode, the power/ground plane is dedicated to the transmission of 2.5Gbps differential signals. Ideally, the differential element does not draw transient current due to its differential characteristics. Therefore, in fact, the target impedance can be higher. By reducing the number of unnecessary PCB layers, it is also possible to avoid exceeding the specification requirements for PCB design.

b. Use Hspice to evaluate components and conduct high-frequency analysis

Although IBIS models are widely used in board level simulation, the analysis based on transistor driver/receiver models is still critical in the evaluation of new PCB components. As IC manufacturers increasingly provide transistor based models in the form of Hspice encryption, Hspice has gradually become the only tool for component evaluation. Such simulation should include loading/unloading package effects, and drive transmission lines of different types and lengths of devices. To this end, manufacturers need to cooperate to provide correct models and modify the models according to the actual components. After the components are determined, the IBIS model can be created and verified according to the final Hspice model and functional indicators. At higher signal rates, such as 10-12.5Gbps, the behavior model is no longer valid. For devices operating in this frequency band, it is meaningless to try to create IBIS models.

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