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Clock stabilization design of pcb protected high-speed A/D converter
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Clock stabilization design of pcb protected high-speed A/D converter

Clock stabilization design of pcb protected high-speed A/D converter
In recent years, foreign research on high-speed A/D converters has been the most active, and some improved structures have appeared in the basIC Flash structure [2], such as supporting circuit structures (such as half flash structure, multi tier structure, multi tier structure) In fact, they are circuit structures composed of multiple flash memory circuit structures and other different forms of functional circuits This structure can make up for the shortcomings of the basic Flash circuit structure. It is a high-speed, high-resolution A/D converter This structure is gradually replacing the long existing synthetic aperture radar and the overall structure, as well as a bit per level circuit structure You will get a A circuit structure calLED Folding (also called Mag Amps structure) This is a Gray code serial output structure These PCB circuit design technologies are rapidly developing, high resolution, and high-performance A/D converters It played a positive role in promoting
PCB proofing
In addition, among the circuit design technologies of high resolution A, D converter and Î - Î circuit structure are very popular circuit design technologies This circuit structure is not only suitable for high resolution low speed or medium speed A/D converters It will gradually replace the structure of synthetic aperture radar and integral circuit. This structure, combined with the channel wide structure, is expected to achieve higher resolution and higher speed A/D converter
PCB proofing clock duty cycle stability circuit
With the continuous expansion and performance improvement of electronic systems in textiles and equipment in the new era, the complexity of electronic systems is also increasing In order to ensure the ability and efficiency of data sampling, control echo, and digital processing of electronic systems, modern military electronic systems/D converters are also getting higher and higher, especially military data communication systems and data acquisition systems The demand for high speed and high resolution A/D converter is being added The clock duty cycle stabilization circuit is used as the core unit of high-speed and high-precision A/D converter plays a vital role in the performance of the converter ⠀™ s signal-to-noise ratio (SNR) and effective bit (ENOB).  Therefore, we must ensure the performance of high-speed and high-precision A/D converters, and ensure that the sampling and coding clocks have appropriate duty cycles and SMAll jitter Therefore, it is necessary to study the clock duty cycle stabilization circuit

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Since the clock duty cycle stabilizing circuit is the core unit of high-speed circuit, high-precision A/D converter, there are few products equipped with independent clock duty cycle stabilizing circuit, and it is only reported in high-speed case, high-precision A/D converter ADI's products can improve the sampling performance mainly due to the improvement of the DCS (duty cycle stabilizer) circuit The DCS circuit is responsible for reducing the jitter of the clock signal. The sampling time depends on the clock In the past, the DCS circuit of each company could only control the jitter at about 0 25p, while the new high-performance products AD9446 and LTC2208 can reduce the jitter to about 50fs Generally, reducing jitter can improve the signal-to-noise ratio, thereby increasing the effective resolution (ENOB: effective number of bits), and can achieve a sampling rate greater than 100 Msps, while achieving 16 bit quantization If the sampling rate is increased without controlling jitter, ENOB will decrease and the required resolution cannot be obtained It is impossible to add quantized digits With the development of high-performance A/D converter, the DCS circuit can be developed to higher speed with less jitter and stability Table 1 lists the clock duty cycle/D converter in foreign A The number of main technologies and parameters of stable circuits
In fact, so far, the 60fs jitter of AD is the smallest At present, the aperture jitter is usually controlled at about 1 ps, and it is of little significance that the jitter is higher than this number or even tens of ps
PCB proofing clock stabilization circuit
From the current research situation at home and abroad, the clock circuit used to stabilize the high-speed ADC is mainly a phase-locked loop (Phase-locked loop, PLL).  The phase-locked system is essentially a closed loop phase control system In short, it is a circuit that can synchronize the output signal with the input signal in terms of frequency and phase. That is, after the system enters the locked state (or synchronized state), the phase difference between the output signal and the input signal of the oscillator is zero or constant Because phase-locked loop has many excellent characteristics, it can be widely used in clock generation and distribution of high-performance processors, system frequency synthesis and conversion, automatic frequency tuning and tracking, bit synchronization selection in digital communication, phase locking, phase-locked frequency multiplication and division, etc
This article proposes a delay-locked loop DLL (Delay-locked loop DLL) design.  In fact, the phase-locked loop mainly uses a phase detector and a filter to monitor the echo clock signal and the input clock signal, and then uses the generated voltage difference to control the voltage controlled oscillator to generate a signal SIMilar to the input clock, and finally achieves the purpose of frequency locking The function of the DLL is to insert delay pulses between the input clock and the echo clock until the rising edges of the two clocks are aligned. When synchronization is achieved, the on-chip delay phase-locked loop DLL can be locked when the edges of the input clock pulse and the echo pulse are aligned After the clock is locked, the circuit is no longer adjusted and there is no difference between the two clocks With this pipeline, the on-chip delay phase-locked loop uses DLL output clock to compensate the time delay caused by the clock distribution network, thus effectively improving the clock source and load Time delay between First, the delay line has less noise than the oscillator This is because the damaged zero crossing point in the waveform disappears at the end of the delay line, and it loops back in the oscillator circuit. Second, it generates more. The delay time changes rapidly within the control voltage variation range in the dynamic link library, that is, the transfer function is only equal to the incremental KBCDL of VCDL In short, the oscillator used in the phase-locked loop has instability and phase offset accumulation. When the compensation clock alone causes time delay in the network, it often reduces the performance of the phase-locked loop Therefore, dynamic link libraries are more stable and faster than PLLs
This PCB board test system will have a new PCB design idea. It will adopt the automatic test system based on USB bus bar and the design idea of virtual instrument, give full play to the role of the computer, and replace the traditional instrument concept with the computer as much as possible. Therefore, reducing the volume of the instrument itself can reduce the development cost, thus improving the development efficiency
After D/conversion, the analog excitation signal required for the test shall be applied to the test system, and then the test circuit shall be sent to the switch matrix through the test bus The switch matrix is connected to the switch matrix, and the switch is controlled by the microprocessor The test PCB is fixed on the needle bed, the excitation signal is applied to the corresponding position of the PCB, the response is measured by the test circuit, and the collected analog quantity is sent to the core control After A/D conversion, the corresponding digital quantity echoes the PCB by the software on the and the PCB determines that the PCB is qualified

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