How to consider the whole signal bandwidth in PCB trace length matching
If you read a lot of PCB design guidelines, especially on parallel protocols and differential pair routing, you will see a lot of information about tracking length matching When tracking length matching is required, your goal is to minimize differential pairs in serial protocols, multiple pairs in parallel protocols (eg PCIe), multiple tracks/pairing in parallel protocols or using the following protocols. The timing difference between any protocol is the source synchronous clock CAD tools make it easier for people to think about what is happening However, what happens to other frequencies? More specifically, what happens to broadband signals? All digital signals are broadband signals with frequency content extending from DC to infinity Due to the large bandwidth of digital signals, which frequency should be used for track length matching? Unfortunately, the frequency used for tracking length matching is not clear. In retrospect, designers need to know how to deal with PCB track length matching and frequency To better understand this, we need to check the technology used in broadband design and how to consider the entire signal bandwidth in track length matching
The Relationship between PCB Trace Length Matching and Difference to Frequency
To properly match the track length and frequency, it is necessary to consider the entire bandwidth of the signal propagating on the track. In the past few years, this has been the research topic of differential serial protocol. Standards such as USB4 put forward specific requirements for broadband signal integrity measurement. Some examples of broadband signal integrity metrics are:
Integrated differential crosstalk
Integrated differential insertion loss
Integrated differential return loss
Integral differential impedance deviation
"Integration" means that specific aspects of signal integrity apply to the entire frequency range of interest. In other words, if we take differential crosstalk as an example, we want to reduce the differential crosstalk between two differential pairs below a certain limit specified in the signal standard. Later we will see why this is important for tracking length matching.
In the time domain, we only focus on the intermediate transition between the high state and the low state (assumed to be binary) at the same time when the two ends of the difference pair cross. Obviously, jitter creates a problem here, that is, it will limit the track length to a certain tolerance range, so you will never achieve a perfect transition at both ends of a pair of wires at the same time. In the frequency domain, we need to consider the following dispersion:
Geometric dispersion: This is due to the boundary conditions and interconnection geometry, which determines how the interconnection impedance changes with the geometry.
Dielectric diffusion: This occurs in the PCB substrate, independent of the geometry of the interconnects on the PCB. It includes dispersion and loss of DK.
Roughness dispersion: due to the causal relationship between the copper roughness model and high-frequency skin effect, this additional dispersion will occur.
Fiber braiding dispersion: The fiber braiding in the PCB laminate produces periodic dispersion changes throughout the interconnection.
Because these dispersion sources always exist in the trace, they cause the impedance, velocity, and all other signal integrity metrics of the actual PCB trace to be a function of frequency.
If you are familiar with transmission line theory, then you know that impedance is closely related to signal speed. Let's take the signal speed of PCB track as an example. The figure below shows the group velocity and phase velocity of an analog stripline with roughness and dispersion. The group velocity and phase velocity of an example stripline signal with copper roughness and dielectric dispersion. Here, we can see that in the wide frequency range from 1MHz to 20GHz, the phase velocity varies greatly, with a coefficient of variation of 2. The change in phase velocity is an important parameter because it is the rate at which different frequency components propagate along the interconnect. With this change, we can see how difficult it is to match the length of PCB trace with the frequency of actual interconnection. We need some way to interpret all frequencies, not just a single frequency chosen arbitrarily.
Broadband length matching and frequency
In order to formulate the length matching metric, we need to consider the allowable length deviation of a given signal standard. We call it time deviation tlim. The function k here is only the propagation constant of the signal on the interconnection, and it is also a function of the frequency caused by dispersion, depending on the length of the allowed timing change. We can adopt a statistical method, using a method called "Lp norm" to deal with the allowed length mismatch. It is not necessary to study the mathematics involved too deeply, just know that this measure is equivalent to calculating the root mean square difference between a function and an average value, which is only a constant difference. This makes it an ideal mathematical tool to solve the changes between some target design values and signal integrity measures (impedance, pulse response attenuation/delay, crosstalk intensity, etc.). Using the Lp norm, we can rewrite the allowed length mismatch according to some upper bounds defined by the timing mismatch limit tlim according to the length change of the allowed timing change.
When using broadband signal integrity measurement: PCB design, the above equation can be regarded as a constraint condition: when determining the size of the transmission line, this may affect the difference between the ends of the difference pair, or the difference between any two traces in the total allowable length deviation High speed parallel protocol As long as the propagation constant of the transmission line is known, the integral can be easily calculated This value can then be calculated using the field solver and the analytical model manually calculated using standard transmission line geometry It is just to calculate some digits. If I use the phase velocity of the analog stripline above, we can see that there is a mismatch in the allowable length between the two parallel traces that are completely isolated at one end. If the allowed value is 2, the timing mismatch is 10ps.07mm Note that for 10ps, this is a large part of the edge rate of many high-speed digital signals For the above analogical stripline, this is equivalent to the allowable length mismatch of 1.3041 mm In conclusion, we have proved that using Lp norm can reduce the frequency of PCB tracking length matching and single measurement If you are a PCB designer, you do not need to perform this calculation manually, you only need to use the correct PCB routing tool set